A fine-grained link-level fault-tolerant mechanism for networks-on-chip

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2010, Pages 447-454

  Vitkovskiy, Arseniy ^a   Soteriou, Vassos ^a   Nicopoulos, Chrysostomos ^b  

^a CYPRUS UNIVERSITY OF TECHNOLOGY   (Cyprus)

^b UNIVERSITY OF CYPRUS   (Cyprus)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP MULTI-PROCESSORS; FAULT MODEL; FAULT TOLERANT ROUTING; FAULT-TOLERANT MECHANISM; FAULTY LINKS; FINITE NUMBER; FULL-SYSTEM SIMULATION; GRACEFUL PERFORMANCE DEGRADATIONS; HARDWARE SYNTHESIS; INTEGRATION CAPABILITY; LOAD-BALANCING ROUTING; MICRO ARCHITECTURES; NETWORK CONNECTIVITY; NETWORKS ON CHIPS; NOC ARCHITECTURES; ON CHIPS; PARALLEL LINKS; PARALLEL SYSTEM; PROPOSED ARCHITECTURES; SILICON TECHNOLOGIES; SINGLE-LINK FAILURES; STATISTICAL LINKS; TRANSMISSION MECHANISMS; UNDERLYING NETWORKS; WIRE FAILURES;

FAULT DETECTION; MICROPROCESSOR CHIPS; ROUTERS; WIRE;

NETWORK ARCHITECTURE;

EID: 78650756156     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2010.5647663     Document Type: Conference Paper

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