Fault-tolerant routing algorithm for network on chip without virtual channels

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2009, Pages 313-321

  Fukushima, Yusuke ^a   Fukushi, Masaru ^a   Horiguchi, Susumu ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSMISSION; DEADLOCK FREENESS; DEADLOCK PROBLEMS; DEADLOCK-FREE ROUTING; DESIGN COMPLEXITY; FAULT-TOLERANT; FAULT-TOLERANT ROUTING ALGORITHM; IRREGULAR MESHES; MESH TOPOLOGIES; MULTI CORE; NETWORK ON CHIP; ROUTING CONTROL; SPACE CONSUMPTION; VIRTUAL CHANNELS;

COMMUNICATION CHANNELS (INFORMATION THEORY); DEFECTS; DISTRIBUTED COMPUTER SYSTEMS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; MAGNETIC FIELD EFFECTS; MICROPROCESSOR CHIPS; PROBABILITY DENSITY FUNCTION; ROUTERS; ROUTING ALGORITHMS; TOPOLOGY; TRAFFIC CONGESTION;

QUALITY ASSURANCE;

EID: 77649303649     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2009.41     Document Type: Conference Paper

References (9)

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