Research challenges for on-chip interconnection networks

IEEE Micro

Volumn 27, Issue 5, 2007, Pages 96-108

  Owens, John D ^a   Dally, William J ^b   Ho, Ron ^c   Jayashima, D N ^d   Keckler, Stephen W ^e   Peh, Li Shuan ^f  

^a Davis   (United States)

^b Stanford University   (United States)

^c SUN MICROSYSTEMS   (United States)

^d INTEL CORPORATION   (United States)

^e UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^f PRINCETON UNIVERSITY   (United States)

Author keywords

Embedded systems; Interconnection networks; Multicore architectures; Network on chip; On chip interconnection networks; System on chip

Indexed keywords

COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; ENGINEERING RESEARCH; MICROPROCESSOR CHIPS;

MULTICORE ARCHITECTURES; MULTICORE PROCESSOR; NETWORK ON-CHIP; ON-CHIP INTERCONNECTION NETWORKS;

INTERCONNECTION NETWORKS;

EID: 36849063126     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2007.4378787     Document Type: Article

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