-
2
-
-
3042671376
-
Guest editors' introduction: Design for yield and reliability
-
May-June
-
Y. Zorian, D. Gizopoulos, C. Vandenberg, P. Magarshack, "Guest editors' introduction: design for yield and reliability", IEEE Design & Test of Computers, May-June 2004, Vol. 21, Issue: 3, pp: 177-182.
-
(2004)
IEEE Design & Test of Computers
, vol.21
, Issue.3
, pp. 177-182
-
-
Zorian, Y.1
Gizopoulos, D.2
Vandenberg, C.3
Magarshack, P.4
-
3
-
-
0141837018
-
Trends and challenges in VLSI circuit reliability
-
July-Aug
-
C. Constantinescu, "Trends and challenges in VLSI circuit reliability", IEEE Micro, July-Aug. 2003, Vol. 23, Issue: 4, pp: 14-19.
-
(2003)
IEEE Micro
, vol.23
, Issue.4
, pp. 14-19
-
-
Constantinescu, C.1
-
4
-
-
3042624706
-
SoC yield optimization via an embedded-memory test and repair infrastructure
-
May-June
-
S. Shoukourian, V. Vardanian, Y. Zorian, "SoC yield optimization via an embedded-memory test and repair infrastructure", IEEE Design & Test of Computers, May-June 2004, Vol. 21, Issue: 3, pp: 200-207.
-
(2004)
IEEE Design & Test of Computers
, vol.21
, Issue.3
, pp. 200-207
-
-
Shoukourian, S.1
Vardanian, V.2
Zorian, Y.3
-
5
-
-
24144461667
-
Performance evaluation and design trade-offs for network-on-chip interconnect architectures
-
Aug
-
P. P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures", IEEE Transactions on Computers, Vol. 54, Issue: 8, Aug. 2005, pp: 1025-1040.
-
(2005)
IEEE Transactions on Computers
, vol.54
, Issue.8
, pp. 1025-1040
-
-
Pande, P.P.1
Grecu, C.2
Jones, M.3
Ivanov, A.4
Saleh, R.5
-
6
-
-
38749099696
-
-
International Technology Roadmap for Semiconductors, 2005 update, http://www.itrs.net/Common/2005ITRS/Home2005.htm
-
International Technology Roadmap for Semiconductors, 2005 update, http://www.itrs.net/Common/2005ITRS/Home2005.htm
-
-
-
-
7
-
-
27344456043
-
The Aethereal network on chip: Concepts, architectures, and implementations
-
Sept-Oct
-
K. Goossens, J. Dielissen, A. Radulescu, "The Aethereal network on chip: concepts, architectures, and implementations", IEEE Design and Test of Computers, Sept-Oct 2005, Vol. 22, Issue: 5, pp:21-1
-
(2005)
IEEE Design and Test of Computers
, vol.22
, Issue.5
, pp. 21-21
-
-
Goossens, K.1
Dielissen, J.2
Radulescu, A.3
-
8
-
-
0017533160
-
Binomial switching networks for concentration and distribution
-
Sep
-
G. Masson, "Binomial switching networks for concentration and distribution", IEEE Transactions on Communications, Sep 1977, Vol. 25, Issue: 9, pp: 873-883.
-
(1977)
IEEE Transactions on Communications
, vol.25
, Issue.9
, pp. 873-883
-
-
Masson, G.1
-
9
-
-
33747731477
-
Architecture scalability of parallel vector computers with a shared memory
-
May
-
E. Dekker, "Architecture scalability of parallel vector computers with a shared memory", IEEE Transactions on Computers, May 1998, Vol. 47, Issue: 5, pp: 614-624.
-
(1998)
IEEE Transactions on Computers
, vol.47
, Issue.5
, pp. 614-624
-
-
Dekker, E.1
-
10
-
-
0026881189
-
On crossbar switch and multiple bus interconnection networks with overlapping connectivity
-
June
-
B. Wilkinson, "On crossbar switch and multiple bus interconnection networks with overlapping connectivity", IEEE Transactions on Computers, June 1992, Vol: 41, Issue: 6, pp:738-746.
-
(1992)
IEEE Transactions on Computers
, vol.41
, Issue.6
, pp. 738-746
-
-
Wilkinson, B.1
-
11
-
-
0025488890
-
optical-fiber crossbar switch operating at 0.85 μm
-
Sep
-
K.D. Pedrotti, S. Beccue, W.J. Haber, B.P. Brar, G. Robinson, M.K. Kilcoyne, "16×16 optical-fiber crossbar switch operating at 0.85 μm", Journal of Lightwave Technology, Sep 1990,Vol. 8, Issue: 9, pp: 1334-1342.
-
(1616)
Journal of Lightwave Technology
, vol.8
, Issue.9
, pp. 1334-1342
-
-
Pedrotti, K.D.1
Beccue, S.2
Haber, W.J.3
Brar, B.P.4
Robinson, G.5
Kilcoyne, M.K.6
-
12
-
-
27344448860
-
Analysis of error recovery schemes for networks on chips
-
Sept.-Oct
-
S. Murali, T. Theocharides, N. Vijaykrishnan, M.J. Irwin, L. Benini, G. De Micheli, "Analysis of error recovery schemes for networks on chips", IEEE Design & Test of Computers, Sept.-Oct. 2005, Vol. 22, Issue: 5, pp: 434-442.
-
(2005)
IEEE Design & Test of Computers
, vol.22
, Issue.5
, pp. 434-442
-
-
Murali, S.1
Theocharides, T.2
Vijaykrishnan, N.3
Irwin, M.J.4
Benini, L.5
De Micheli, G.6
-
13
-
-
18144426826
-
Routability and fault tolerance of FPGA interconnect architectures
-
J. Huang; M.B. Tahoori, F. Lombardi, "Routability and fault tolerance of FPGA interconnect architectures", Proceedings of the IEEE International Test Conference, ITC 2004, pp: 479-488.
-
Proceedings of the IEEE International Test Conference
, vol.ITC 2004
, pp. 479-488
-
-
Huang, J.1
Tahoori, M.B.2
Lombardi, F.3
-
14
-
-
0023962947
-
Critical area and critical levels calculation in IC yield modeling
-
Feb
-
S. Gandemer, B.C. Tremintin, J.-J. Charlot, "Critical area and critical levels calculation in IC yield modeling", IEEE Transactions on Electron Devices, Feb. 1988, Vol. 35, Issue: 2, pp: 158-166.
-
(1988)
IEEE Transactions on Electron Devices
, vol.35
, Issue.2
, pp. 158-166
-
-
Gandemer, S.1
Tremintin, B.C.2
Charlot, J.-J.3
-
16
-
-
0032028114
-
Regular sparse crossbar concentrators
-
March
-
W. Guo, A.Y. Oruc, "Regular sparse crossbar concentrators", IEEE Transactions on Computers, March 1998, Vol. 47, Issue: 3, pp: 363-368.
-
(1998)
IEEE Transactions on Computers
, vol.47
, Issue.3
, pp. 363-368
-
-
Guo, W.1
Oruc, A.Y.2
-
17
-
-
0030243566
-
Crosspoint complexity of sparse crossbar concentrators
-
Sept
-
A. Y. Oruc, H.M. Huang, "Crosspoint complexity of sparse crossbar concentrators", IEEE Transactions on Information Theory, Sept. 1996, Vol. 42, Issue: 5, pp: 1466-1471.
-
(1996)
IEEE Transactions on Information Theory
, vol.42
, Issue.5
, pp. 1466-1471
-
-
Oruc, A.Y.1
Huang, H.M.2
-
18
-
-
33144475037
-
A test structure for contact and via failure analysis in deep-submicrometer CMOS technologies
-
Feb
-
A. Cabrini, D. Cantarelli, P. Cappelletti, R. Casiraghi, A. Maurelli, Marco Pasotti, P.L. Rolandi, G. Torelli, "A test structure for contact and via failure analysis in deep-submicrometer CMOS technologies", IEEE Transactions on Semiconductor Manufacturing, Feb. 2006, Vol. 19, Issue: 1, pp: 57-66.
-
(2006)
IEEE Transactions on Semiconductor Manufacturing
, vol.19
, Issue.1
, pp. 57-66
-
-
Cabrini, A.1
Cantarelli, D.2
Cappelletti, P.3
Casiraghi, R.4
Maurelli, A.5
Pasotti, M.6
Rolandi, P.L.7
Torelli, G.8
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