-
1
-
-
84948696213
-
A network on chip architecture and design methodology
-
S. Kumar, A. Jantsch, J. P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, A. Hemani, "A Network on Chip Architecture and Design Methodology", Proc. ISVLSI, pp. 117-122, April 2002.
-
(2002)
Proc. ISVLSI
, pp. 117-122
-
-
Kumar, S.1
Jantsch, A.2
Soininen, J.P.3
Forsell, M.4
Millberg, M.5
Oberg, J.6
Tiensyrja, K.7
Hemani, A.8
-
2
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
DOI 10.1109/2.976921
-
L. Benini, G. De Micheli, "Networks on Chips: A New SoC Paradigm", IEEE Computers, Vol.35(1), pp. 70-78, Jan. 2002. (Pubitemid 34069383)
-
(2002)
Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
De Micheli, G.2
-
3
-
-
4544376708
-
Fault-tolerant algorithms for network-on-chip interconnect
-
M. Pirretti, G.M. Link, R.R. Brooks, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, "Fault-tolerant algorithms for network-on-chip interconnect", Proc. IEEE Computer society Annual Symposium on VLSI (ISVLSI04), Feb. 2004, pp. 46- 51
-
(2004)
Proc. IEEE Computer society Annual Symposium on VLSI (ISVLSI04)
, pp. 46-51
-
-
Pirretti, M.1
Link, G.M.2
Brooks, R.R.3
Vijaykrishnan, N.4
Kandemir, M.5
Irwin, M.J.6
-
5
-
-
27344448860
-
Analysis of error recovery schemes for networks on chips
-
DOI 10.1109/MDT.2005.104
-
S. Msurali et al., "Analysis of Error Recovery Schemes for Networkson- Chips", IEEE Design and Test of Computers, Vol.22(5), pp. 434-442, Sep-Oct 2005. (Pubitemid 41522731)
-
(2005)
IEEE Design and Test of Computers
, vol.22
, Issue.5
, pp. 434-442
-
-
Murali, S.1
Theocharides, T.2
Vijaykrishnan, N.3
Irwin, M.J.4
Benini, L.5
De Micheli, G.6
-
6
-
-
1142287741
-
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
-
H. Zimmer, A. Jantsch,"A Fault Model Notation and Error-Control Scheme for switch-to-Switch Buses in a Network-on-Chip", Proc. ISSS/CODES, pp. 188- 193, Sept 2003.
-
(2003)
Proc. ISSS/CODES
, pp. 188-193
-
-
Zimmer, H.1
Jantsch, A.2
-
8
-
-
0034848112
-
Route packets, not wires: on-chip interconnection networks
-
W. J. Dally, B. Towles, "Route packets, not wires: on-chip interconnection networks", In Proc. Design Automatin Conf. (DAC), pp 684-689, June 2001.
-
(2001)
Proc. Design Automatin Conf. (DAC)
, pp. 684-689
-
-
Dally, W.J.1
Towles, B.2
-
9
-
-
33845589989
-
Exploring fault-tolerant network-on-chip architectures
-
D. Park, C. Nicopoulos; J. Kim, N. Vijaykrishnan, C.R. Das, "Exploring Fault-Tolerant Network-on-Chip Architectures", Inte. Conf. on Dependable Systems and Networks (DSN) 2006, pp. 93.
-
(2006)
Inte. Conf. on Dependable Systems and Networks (DSN)
, pp. 93
-
-
Park, D.1
Nicopoulos, C.2
Kim, J.3
Vijaykrishnan, N.4
Das, C.R.5
-
11
-
-
33846945395
-
Fault-tolerant routing schemes in RDT(2,2,1)/-based interconnection network for networks-on-chip design
-
M. Yang, T. Li, Y. Jiang, Y. Yang, "Fault-tolerant routing schemes in RDT(2,2,1)/-based interconnection network for networks-on-chip design", 8th Inte. Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 2005), pp. 6, Dec 2005.
-
(2005)
8th Inte. Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 2005)
, pp. 6
-
-
Yang, M.1
Li, T.2
Jiang, Y.3
Yang, Y.4
-
12
-
-
27944452666
-
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
-
San Diego, California, USA
-
S. Manolache, P. Eles, Z. Peng, "Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC", Proc. of the 42nd annual Conf. on Design Automation (DAC 2005), San Diego, California, USA.
-
(2005)
Proc. of the 42nd annual Conf. on Design Automation (DAC)
-
-
Manolache, S.1
Eles, P.2
Peng, Z.3
-
14
-
-
0034245046
-
Toward achieving energy efficiency in presence of deep submicron noise
-
DOI 10.1109/92.863617
-
R. Hegde and N.R. Shanbhag, "Towards Achieving Energy Efficiency in Presence of Deep Submicron Noise," IEEE Trans. VLSI Systems, vol.8, no. 4, Aug. 2000, pp. 379-391. (Pubitemid 30934986)
-
(2000)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.8
, Issue.4
, pp. 379-391
-
-
Hegde, R.1
Shanbhag, N.R.2
-
15
-
-
34247277804
-
A multipath routing strategy with guaranteed in-order packet delivery and faulttolerance for networks on chip
-
San Francisco, Calif, USA, July
-
S. Murali, D. Atienza, L. Benini, and G. De Micheli, "A multipath routing strategy with guaranteed in-order packet delivery and faulttolerance for networks on chip," in Proc. of the 43rd ACM/IEEE Design Automation Conf. (DAC '06), pp. 845-848, San Francisco, Calif, USA, July 2006.
-
(2006)
Proc. of the 43rd ACM/IEEE Design Automation Conf. (DAC '06)
, pp. 845-848
-
-
Murali, S.1
Atienza, D.2
Benini, L.3
De Micheli, G.4
-
16
-
-
34247238842
-
Evaluating SEU and crosstalk effects in network-on-chip routers
-
DOI 10.1109/IOLTS.2006.33, 1655546, Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium
-
A. P. Frantz, L. Carro, É.F. Cota, F. L. Kastensmidt, "Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers", IOLTS 2006: 191-192 (Pubitemid 46603896)
-
(2006)
Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium
, vol.2006
, pp. 191-192
-
-
Frantz, A.P.1
Carro, L.2
Cota, E.3
Kastensmidt, F.L.4
-
17
-
-
69949090868
-
Testing SoC interconnects for signal integrity using boundary scan
-
M. H. Tehranipour, N. Ahmed, M. Nourani, "Testing SoC Interconnects for Signal Integrity Using Boundary Scan", VTS 2003: 158-172
-
(2003)
VTS
, pp. 158-172
-
-
Tehranipour, M.H.1
Ahmed, N.2
Nourani, M.3
-
18
-
-
84954417739
-
Towards on-chip faulttolerant communication
-
T. Dumitras, S. Kerner, and R. Marculescu, "Towards on-chip faulttolerant communication," in Proc. of the Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 225-232, 2003.
-
(2003)
Proc. of the Asia and South Pacific Design Automation Conf. (ASP-DAC)
, pp. 225-232
-
-
Dumitras, T.1
Kerner, S.2
Marculescu, R.3
-
20
-
-
4544376708
-
Fault tolerant algorithms for network-on-chip interconnect
-
M. Pirretti, G. M. Link, R. R. Brooks, N. Vijaykrishnan, M. Kandemir, and I. M. J. Fault tolerant algorithms for network-on-chip interconnect. In Proc. of the ISVLSI, 2004.
-
(2004)
Proc. of the ISVLSI
-
-
Pirretti, M.1
Link, G.M.2
Brooks, R.R.3
Vijaykrishnan, N.4
Kandemir, M.5
-
21
-
-
0027837827
-
A new theory of deadlock-free adaptive routing in wormhole networks
-
J. Duato, "A new theory of deadlock-free adaptive routing in wormhole networks," Parallel and Distributed Systems, IEEE Transactions on, vol. 4, pp. 1320-1331, 1993
-
(1993)
Parallel and Distributed Systems, IEEE Transactions on
, vol.4
, pp. 1320-1331
-
-
Duato, J.1
|