-
1
-
-
1642323389
-
An analytical method for approximate performance evaluation of binary linear block codes
-
February
-
A. Abedi, A. K. Khandani, "An Analytical Method for Approximate Performance Evaluation of Binary Linear Block Codes" in IEEE Transactions on Communications, Vol. 52, February 2004.
-
(2004)
IEEE Transactions on Communications
, vol.52
-
-
Abedi, A.1
Khandani, A.K.2
-
4
-
-
0032183145
-
The art of signaling: Fifty years of coding theory
-
October
-
A. R. Calderbank, "The Art of Signaling: Fifty Years of Coding Theory" in IEEE Transactions on Information Theory, Vol. 44, October 1998.
-
(1998)
IEEE Transactions on Information Theory
, vol.44
-
-
Calderbank, A.R.1
-
5
-
-
0032183996
-
Applications of error-control coding
-
October
-
D. J. Costello, J. Hagenauer, H. Imai, S. B. Wicker, "Applications of Error-Control Coding" in IEEE Transactions on Information Theory, Vol. 44, October 1998.
-
(1998)
IEEE Transactions on Information Theory
, vol.44
-
-
Costello, D.J.1
Hagenauer, J.2
Imai, H.3
Wicker, S.B.4
-
6
-
-
0032183996
-
Applications of error-control coding
-
October
-
D. J. Costello, J. Hagenauer, H. Imai, S. B. Wicker, "Applications of Error-Control Coding" in IEEE Transactions on Information Theory, Vol. 6, October 1998.
-
(1998)
IEEE Transactions on Information Theory
, vol.6
-
-
Costello, D.J.1
Hagenauer, J.2
Imai, H.3
Wicker, S.B.4
-
9
-
-
0028550520
-
Evaluation of the performance of binary error correcting codes over gaussian QAM channels
-
November
-
F. Guida, E. Montolivo, G. M. Pascetti, "Evaluation of the Performance of Binary Error Correcting Codes over Gaussian QAM Channels" in Electronics Letters, Vol. 30, November 1994.
-
(1994)
Electronics Letters
, vol.30
-
-
Guida, F.1
Montolivo, E.2
Pascetti, G.M.3
-
10
-
-
84892192223
-
Coding theory and cryptography the essentials
-
D. R. Hankerson, D. G. Hoffman, D. A. Leonard, C. C. Lindner, K. T. Phelps, C. A. Rodger, J. R. Wall, "Coding Theory and Cryptography the essentials", Marcel Dekker Inc., 1991.
-
(1991)
Marcel Dekker Inc
-
-
Hankerson, D.R.1
Hoffman, D.G.2
Leonard, D.A.3
Lindner, C.C.4
Phelps, K.T.5
Rodger, C.A.6
Wall, J.R.7
-
14
-
-
0022811644
-
On the existence of optimum cyclic burst-correcting codes
-
November
-
A. S. A. G. Khaled, R. J. McEliece, A. M. Odlyzka, H. C. A. von Tilborg, "On the Existence of Optimum Cyclic Burst-Correcting Codes" in IEEE Transactions on Information Theory, Vol. 32, November 1986.
-
(1986)
IEEE Transactions on Information Theory
, vol.32
-
-
Khaled, A.S.A.G.1
McEliece, R.J.2
Odlyzka, A.M.3
Von Tilborg, H.C.A.4
-
21
-
-
0029256342
-
List and soft symbol output viterbi algorithms: Extensions and comparisons
-
February/March/April, 3
-
C. Nill, C. E. W. Sundberg, "List and Soft Symbol Output Viterbi Algorithms: Extensions and Comparisons" in IEEE Transactions on Communications, Vol. 2/3/4, February/March/April 1995.
-
(1995)
IEEE Transactions on Communications
, vol.2-4
-
-
Nill, C.1
Sundberg, C.E.W.2
-
27
-
-
84856043672
-
A mathematical theory of communication
-
C. E. Shannon, "A Mathematical Theory of Communication" in Bell System Tech. J., 1948.
-
(1948)
Bell System Tech. J
-
-
Shannon, C.E.1
-
35
-
-
0035247672
-
A reed-solomon product-code (RS-PC) decoder chip for DVD applications
-
February
-
H. C. Chang, C. B. Shung, C. Y. Lee, "A Reed-Solomon product-code (RS-PC) decoder chip for DVD Applications" in IEEE Journal of Solid State Circuits, Vol. 36, February 2001.
-
(2001)
IEEE Journal of Solid State Circuits
, vol.36
-
-
Chang, H.C.1
Shung, C.B.2
Lee, C.Y.3
-
38
-
-
84892335321
-
-
Springer- Verlag
-
G. Cohen, T. Mora, O. Moreno, "Applied Algebra, Algebraic Algorithms and Error-Correcting Codes: 10th International Symposium AAECC-10 San Juan de Puerto Rico", Springer- Verlag, 1993.
-
(1993)
Applied Algebra, Algebraic Algorithms and Error-Correcting Codes: 10th International Symposium AAECC-10 San Juan de Puerto Rico
-
-
Cohen, G.1
Mora, T.2
Moreno, O.3
-
39
-
-
0034316125
-
On the equivalence of the belekamp-massey and the euclidean algorithms for decoding
-
Nov
-
A. E. Heydtmann, J. M. Jensen, "On the Equivalence of the Belekamp-Massey and the Euclidean Algorithms for Decoding" in IEEE Transactions on Information Theory, Vol. 46, Nov. 2000.
-
(2000)
IEEE Transactions on Information Theory
, vol.46
-
-
Heydtmann, A.E.1
Jensen, J.M.2
-
43
-
-
0035355188
-
Reed-solomon decoding algorithms for digital audio broadcasting in the AM band
-
June
-
J. N. Laneman, C. E. W. Sundberg, "Reed-Solomon Decoding Algorithms for Digital Audio Broadcasting in the AM Band" in IEEE Transactions Broadcasting, Vol. 47, June 2001.
-
(2001)
IEEE Transactions Broadcasting
, vol.47
-
-
Laneman, J.N.1
Sundberg, C.E.W.2
-
45
-
-
84937740421
-
Shift-register synthesis and BCH decoding
-
January
-
J. Massey, "Shift-Register Synthesis and BCH Decoding" in IEEE Transactions on Information Theory, Vol. 15, January 1969.
-
(1969)
IEEE Transactions on Information Theory
, vol.15
-
-
Massey, J.1
-
46
-
-
84892244336
-
-
Springer-Verlag
-
H. F. Mattson, T. Mora, T. R. N. Rao, "Applied Algebra, Algebraic Algorithms and Error- Correcting Codes: 9th International Symposium AAECC-9 New Orleans, USA", Springer-Verlag, 1992.
-
(1992)
Applied Algebra, Algebraic Algorithms and Error- Correcting Codes: 9th International Symposium AAECC-9 New Orleans, USA
-
-
Mattson, H.F.1
Mora, T.2
Rao, T.R.N.3
-
50
-
-
0001174154
-
Polynomial codes over certain finite fields
-
June
-
I. S. Reed, G. Solomon, "Polynomial Codes over Certain Finite Fields", Journal of SIAM, Vol. 8, June 1960.
-
(1960)
Journal of SIAM
, vol.8
-
-
Reed, I.S.1
Solomon, G.2
-
51
-
-
84892286154
-
-
Tokio, Japan, Springer-Verlag
-
S. Sakata, "Applied Algebra, Algebraic Algorithms and Error-Correcting Codes: 8th International Conference AAECC-8 Tokio, Japan", Springer-Verlag, 1991.
-
(1991)
Applied Algebra, Algebraic Algorithms and Error-Correcting Codes: 8th International Conference AAECC
, vol.8
-
-
Sakata, S.1
-
55
-
-
0020906580
-
An improved frequency compensation technique for CMOS operational amplifiers
-
November
-
B. K. Ahuja, "An Improved Frequency Compensation Technique for CMOS Operational Amplifiers", Journal of Solid-State Circuits, Vol. SC-18, pp. 629-633, November 1983.
-
(1983)
Journal of Solid-State Circuits
, vol.SC-18
, pp. 629-633
-
-
Ahuja, B.K.1
-
56
-
-
0019590240
-
An analytical expression for the threshold voltage of a small geometry MOSFET
-
L. A. Akerst, "An Analytical Expression for the Threshold Voltage of a Small Geometry MOSFET", Solid State Electronics, Vol. 24, pp. 621-627, 1981.
-
(1981)
Solid State Electronics
, vol.24
, pp. 621-627
-
-
Akerst, L.A.1
-
58
-
-
84891472966
-
-
United States Patents 5, 039, 882, August 13
-
H. Arakawa, "Address Decoder Circuit for Non-Volatile Memory", United States Patents 5, 039, 882, August 13, 1991.
-
(1991)
Address Decoder Circuit for Non-Volatile Memory
-
-
Arakawa, H.1
-
59
-
-
0034453383
-
Advance flash memory technology and trends for file storage application
-
S. Aritome, "Advance Flash Memory Technology and Trends for File Storage Application", in IEDM Tech. Dig., pp. 763-766, 2000.
-
(2000)
IEDM Tech. Dig
, pp. 763-766
-
-
Aritome, S.1
-
60
-
-
0027591522
-
Reliability issues of flash memory cells
-
May
-
S. Aritome, R. Shirota, G. Hemink, T. Endoh, F. Masoka, "Reliability Issues of Flash Memory Cells", Proc. IEEE, Vol. 81, No. 5, pp. 776-788, May 1993.
-
(1993)
Proc. IEEE
, vol.81
, Issue.5
, pp. 776-788
-
-
Aritome, S.1
Shirota, R.2
Hemink, G.3
Endoh, T.4
Masoka, F.5
-
62
-
-
0034314527
-
A channel-erasing 1.8 V-only 32-Mb nor flash EEPROM with a bitline direct sensing scheme
-
November
-
S. Atsumi et al., "A Channel-Erasing 1.8 V-Only 32-Mb NOR Flash EEPROM with a Bitline Direct Sensing Scheme", IEEE Journal of Solid-State Circuits, Vol. SC-35, pp. 1648-1654, November 2000.
-
(2000)
IEEE Journal of Solid-State Circuits
, vol.SC-35
, pp. 1648-1654
-
-
Atsumi, S.1
-
63
-
-
0004427465
-
A triple-well architecture for low voltage operation in submicron CMOS devices
-
(Eds.), Bologna, Italy
-
C. Auricchio et al., "A Triple-Well Architecture for Low Voltage Operation in Submicron CMOS Devices", (Eds.), Proc. ESSDERC 96, Bologna, Italy, p. 613, 1996.
-
(1996)
Proc. ESSDERC 96
, pp. 613
-
-
Auricchio, C.1
-
65
-
-
0036089046
-
A new reliability model for post-cycling charge retention of flash memories
-
H.P. Belgal et al., "A New Reliability Model for Post-cycling Charge Retention of Flash Memories", Proc. IRPS, pp. 7-20, 2002.
-
(2002)
Proc. IRPS
, pp. 7-20
-
-
Belgal, H.P.1
-
66
-
-
0043279676
-
Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime
-
June
-
A. Bellaouar et al., "Bootstrapped Full-Swing BiCMOS/BiNMOS Logic Circuits for 1.2-3.3 V Supply Voltage Regime", IEEE Journal of Solid-State Circuits, Vol. 30, No. 6, June 1995.
-
(1995)
IEEE Journal of Solid-State Circuits
, vol.30
, Issue.6
-
-
Bellaouar, A.1
-
67
-
-
3142773890
-
Introduction to flash memory
-
April
-
R. Bez, "Introduction to Flash Memory", IEEE Proceeding of the, Vol. 91, No. 4, pp. 489-502, April 2003.
-
(2003)
IEEE Proceeding of the
, vol.91
, Issue.4
, pp. 489-502
-
-
Bez, R.1
-
68
-
-
33646848810
-
Depletion mechanism of flash cell induced by parasitic drain stress contidion
-
R. Bez et al., "Depletion Mechanism of Flash Cell Induced by Parasitic Drain Stress Contidion", VLSI Technology Symposium, 1994.
-
(1994)
VLSI Technology Symposium
-
-
Bez, R.1
-
69
-
-
3142773890
-
Introduction to flash memory
-
R. Bez et al., "Introduction to Flash Memory", Proceedings of the IEEE, Vol. 91, pp. 554-568, 2003.
-
(2003)
Proceedings of the IEEE
, vol.91
, pp. 554-568
-
-
Bez, R.1
-
72
-
-
0003797611
-
-
eds., New York, NY: IEEE Press
-
W. D. Brown, J. E. Brewer, eds., "Nonvolatile Semiconductor Memory Technology", New York, NY: IEEE Press, 1998.
-
(1998)
Nonvolatile Semiconductor Memory Technology
-
-
Brown, W.D.1
Brewer, J.E.2
-
75
-
-
0035498473
-
Architecture of non volatile memory with multi-Bit cells
-
November
-
G. Campardo, R. Micheloni, "Architecture of Non volatile Memory with Multi-Bit Cells", Elsevier Science, Microelectronic Engineering, Vol. 59, No. 1-4, pp. 173-181, November 2001.
-
(2001)
Elsevier Science, Microelectronic Engineering
, vol.59
, Issue.1-4
, pp. 173-181
-
-
Campardo, G.1
Micheloni, R.2
-
76
-
-
85081073626
-
Scanning the special issue on flash memory technology
-
April
-
G. Campardo, R. Micheloni, "Scanning the Special Issue on Flash Memory Technology", IEEE Proceeding of the, Vol. 91, No. 4, pp. 483-488, April 2003.
-
(2003)
IEEE Proceeding of the
, vol.91
, Issue.4
, pp. 483-488
-
-
Campardo, G.1
Micheloni, R.2
-
77
-
-
84891390901
-
-
USA Patent No. 6, 018, 255
-
G. Campardo, R. Micheloni, S. Commodaro, "Line Decoder for Memory Devices", USA Patent No. 6, 018, 255.
-
Line Decoder for Memory Devices
-
-
Campardo, G.1
Micheloni, R.2
Commodaro, S.3
-
78
-
-
84891468617
-
-
USA Patent No. 5, 903, 498
-
G. Campardo, R. Micheloni, S. Commodaro, "Low Supply Voltage Nonvolatile Memory Device with Voltage Boosting", USA Patent No. 5, 903, 498.
-
Low Supply Voltage Nonvolatile Memory Device with Voltage Boosting
-
-
Campardo, G.1
Micheloni, R.2
Commodaro, S.3
-
79
-
-
84891446473
-
-
USA Patent No. 6, 128, 225
-
G. Campardo, R. Micheloni, S. Commodaro, "Method and Circuit for Reading Low- Supply-Voltage Nonvolatile Memory Cells", USA Patent No. 6, 128, 225.
-
Method and Circuit for Reading Low- Supply-Voltage Nonvolatile Memory Cells
-
-
Campardo, G.1
Micheloni, R.2
Commodaro, S.3
-
80
-
-
84891428554
-
-
USA Patent No. 5, 805, 500
-
G. Campardo, R. Micheloni, M. MacCarrone, "Circuit and Method for Generating a Read Reference Signal for Nonvolatile Memory Cells", USA Patent No. 5, 805, 500.
-
Circuit and Method for Generating a Read Reference Signal for Nonvolatile Memory Cells
-
-
Campardo, G.1
Micheloni, R.2
MacCarrone, M.3
-
81
-
-
84891477243
-
-
USA Patent No. 5, 886, 925
-
G. Campardo, R. Micheloni, M. Maccarrone, "Read Circuit and Method for Nonvolatile Memory Cells with an Equalizing Structure", USA Patent No. 5, 886, 925.
-
Read Circuit and Method for Nonvolatile Memory Cells with An Equalizing Structure
-
-
Campardo, G.1
Micheloni, R.2
Maccarrone, M.3
-
85
-
-
0034430972
-
A 40 mm2 3V 50 MHz 64 Mb 4-level Cell nor type flash memory
-
San Francisco
-
G. Campardo et al., "A 40 mm2 3V 50 MHz 64 Mb 4-level Cell NOR Type Flash Memory", 2000 ISSCC, San Francisco.
-
(2000)
ISSCC
-
-
Campardo, G.1
-
87
-
-
0034316131
-
40- 3-V-only 50-MHz 64-Mb 2-b/cell CHE nor flash memory
-
November
-
G. Campardo et al., "40- 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR Flash Memory", IEEE Journal of Solid-State Circuits, Vol. SC-35, No. 11, pp. 1655-1667, November. 2000.
-
(2000)
IEEE Journal of Solid-State Circuits
, vol.SC-35
, Issue.11
, pp. 1655-1667
-
-
Campardo, G.1
-
88
-
-
20444483395
-
An overview of flash architectural developments
-
April
-
G. Campardo et al., "An overview of Flash Architectural Developments", IEEE Proceeding of the, Vol. 91, No. 4, pp. 523-536, April 2003.
-
(2003)
IEEE Proceeding of the
, vol.91
, Issue.4
, pp. 523-536
-
-
Campardo, G.1
-
89
-
-
0002646843
-
Flash memory reliability
-
P. Cappelletti et al. Ed Kluwer
-
P. Cappelletti, A. Modelli, "Flash Memory Reliability", in Flash Memory, P. Cappelletti et al., Ed Kluwer, 1999.
-
(1999)
Flash Memory
-
-
Cappelletti, P.1
Modelli, A.2
-
91
-
-
0013033577
-
-
Kluwer Academic Publishers
-
E. Charbon, R. Gharpurey, P. Miliozzi, R. G. Meyer, A. Sangiovanni-Vincentelli, "SUBSTRATE NOISE - Analysis and Optimization for IC design", Kluwer Academic Publishers, 2001.
-
(2001)
SUBSTRATE NOISE - Analysis and Optimization for IC Design
-
-
Charbon, E.1
Gharpurey, R.2
Miliozzi, P.3
Meyer, R.G.4
Sangiovanni-Vincentelli, A.5
-
92
-
-
0019603042
-
Coupling capacitance for two-dimensional wires
-
August
-
R. L. M. Dang, N. Shigyo, "Coupling Capacitance for Two-Dimensional Wires", IEEE Electron Deviced Letters, Vol. EDL-2, No. 8, pp. 196-197, August 1981.
-
(1981)
IEEE Electron Deviced Letters
, vol.EDL-2
, Issue.8
, pp. 196-197
-
-
Dang, R.L.M.1
Shigyo, N.2
-
93
-
-
0024897857
-
A 5V-only 256K bit CMOS frlash EEPROM
-
S. D'Arrigo et al., "A 5V-Only 256K Bit CMOS Flash EEPROM", ISSCC 89, pp. 132-133.
-
ISSCC 89
, pp. 132-133
-
-
D'Arrigo, S.1
-
94
-
-
1542732811
-
High speed sensing scheme for CMOS DRAM's
-
February
-
S. H. Dhong et al., "High Speed Sensing Scheme for CMOS DRAM's", IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, pp. 34-40, February 1988.
-
(1988)
IEEE Journal of Solid-State Circuits
, vol.23
, Issue.1
, pp. 34-40
-
-
Dhong, S.H.1
-
95
-
-
0027545680
-
Double and triple charge pump for power IC dynamic models which take parasitic effects into account
-
February
-
G. Di Cataldo, G. Palumbo, "Double and Triple Charge Pump for Power IC Dynamic Models Which Take Parasitic Effects into Account", IEEE Transaction Circuits System, Vol. CAS-40, pp. 92-101, February 1993.
-
(1993)
IEEE Transaction Circuits System
, vol.CAS-40
, pp. 92-101
-
-
Cataldo, G.D.1
Palumbo, G.2
-
96
-
-
84885847112
-
On-chip high voltage generation in MNOS integrated circuits using an improved voltage multiplier technique
-
J. Dickson, "On-Chip High Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique", IEEE Journal of Solid-State Circuits.
-
IEEE Journal of Solid-State Circuits
-
-
Dickson, J.1
-
97
-
-
0028312527
-
Flash EEPROM Disturb Mechanisms
-
April
-
C. Dunn et al., "Flash EEPROM Disturb Mechanisms", in Proc. Int. Rel. Phys. Symp., pp. 299-308, April 1994.
-
(1994)
Proc. Int. Rel. Phys. Symp
, pp. 299-308
-
-
Dunn, C.1
-
98
-
-
0019544106
-
Hot electron injection into the oxide in n-channel MOS devices
-
March, Vol. SC-11, 374-378, June 1976
-
B. Eitan and D. Frohman-Bentchkowski, "Hot Electron Injection into the Oxide in n-channel MOS Devices", IEEE Trans. Electron Devices, Vol. ED-28, pp. 328-340, March 1981. Vol. SC-11, No. 3, pp. 374-378, June 1976.
-
(1981)
IEEE Trans. Electron Devices
, vol.ED-28
, Issue.3
, pp. 328-340
-
-
Eitan, B.1
Frohman-Bentchkowski, D.2
-
99
-
-
0037630791
-
A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write
-
February
-
D. Elmhurst et al., "A 1.8 V 128 Mb 125 MHz Multi-level Cell Flash Memory with Flexible Read While Write", ISSCC Dig. Tech. Papers, pp. 286-287, February 2003.
-
(2003)
ISSCC Dig. Tech. Papers
, pp. 286-287
-
-
Elmhurst, D.1
-
100
-
-
0015048661
-
Memory behavior in a floating gate avalanche-injection MOS (FAMOS) ftructure
-
D. Frohman-Bentchkowsi, "Memory Behavior in a Floating Gate Avalanche-Injection MOS (FAMOS) Structure", Appl. Phys. Lett., Vol. 18, pp. 332-334, 1971.
-
(1971)
Appl. Phys. Lett
, vol.18
, pp. 332-334
-
-
Frohman-Bentchkowsi, D.1
-
101
-
-
0016072040
-
FAMOS-A new semiconductor charge storage device
-
D. Frohman-Bentchkowsi, "FAMOS-A New Semiconductor Charge Storage Device", Solid State Electron, Vol. 17, pp. 517-520, 1974.
-
(1974)
Solid State Electron
, vol.17
, pp. 517-520
-
-
Frohman-Bentchkowsi, D.1
-
102
-
-
33646843945
-
Survey on flash technology with specific attention to the critical process parameters related to manufacturing
-
April
-
G. Ginami. et al., "Survey on Flash Technology with Specific Attention to the Critical Process Parameters Related to Manufacturing", IEEE Proceeding of the, Vol. 91, No. 4, pp. 503-522, April 2003.
-
(2003)
IEEE Proceeding of the
, vol.91
, Issue.4
, pp. 503-522
-
-
Ginami, G.1
-
103
-
-
0020268431
-
MOS operational amplifier design- A tutorial overview
-
December
-
P. R. Gray, R.G. Meyer, "MOS Operational Amplifier Design- A Tutorial Overview", IEEE Journal of Solid State Circuits, Vol. SC-17, No. 6, pp. 969-982, December 1982.
-
(1982)
IEEE Journal of Solid State Circuits
, vol.SC-17
, Issue.6
, pp. 969-982
-
-
Gray, P.R.1
Meyer, R.G.2
-
105
-
-
3142694456
-
Program schemes for multilevel flash memories
-
April
-
M. Grossi et al., "Program Schemes for Multilevel Flash Memories", IEEE Proceeding of the, Vol. 91, No. 4, pp. 594-601, April 2003.
-
(2003)
IEEE Proceeding of the
, vol.91
, Issue.4
, pp. 594-601
-
-
Grossi, M.1
-
106
-
-
84891399404
-
-
U.S. Patent No. 5, 077, 691, October 23
-
S. S. Haddadi et al., Flash E2PROM Array with Negative Gate Voltage Erase Operation, U.S. Patent No. 5, 077, 691, October 23, 1989.
-
(1989)
Flash E2PROM Array with Negative Gate Voltage Erase Operation
-
-
Haddadi, S.S.1
-
107
-
-
14844342748
-
-
Boston, MA: Kluwer Academic Publishers, Ch. 5
-
T. P. Haraszti, CMOS Memory Circuits. Boston, MA: Kluwer Academic Publishers, Ch. 5, 2000.
-
(2000)
CMOS Memory Circuits
-
-
Haraszti, T.P.1
-
108
-
-
0024610684
-
Twisted bit-line architectures for multi-megabit DRAM's
-
February
-
H. Hidaka et al., "Twisted Bit-Line Architectures for Multi-Megabit DRAM's", IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, pp. 21-27, February 1989.
-
(1989)
IEEE Journal of Solid-State Circuits
, vol.24
, Issue.1
, pp. 21-27
-
-
Hidaka, H.1
-
109
-
-
34547277251
-
An experimental large-capacity semiconductor file memory using 16-levels/cell storage
-
February
-
M. Horiguchi, M. Aoki, Y. Nakagome, S. Ikenaga, K. Shimohigashi, "An Experimental Large-Capacity Semiconductor File Memory Using 16-Levels/Cell Storage", IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, pp. 27-33, February 1988.
-
(1988)
IEEE Journal of Solid-State Circuits
, vol.23
, Issue.1
, pp. 27-33
-
-
Horiguchi, M.1
Aoki, M.2
Nakagome, Y.3
Ikenaga, S.4
Shimohigashi, K.5
-
110
-
-
0018732586
-
Lucky-electron model for channel hot-electron emission
-
December
-
C. Hu, "Lucky-Electron Model for Channel Hot-Electron Emission", 1979 IEDM Tech. Dig., pp. 22-25, December 1979.
-
(1979)
1979 IEDM Tech. Dig
, pp. 22-25
-
-
Hu, C.1
-
111
-
-
0027594079
-
Future CMOS scaling and reliability
-
C. Hu, "Future CMOS Scaling and Reliability", Proceedings of the IEEE, Vol. 81, pp. 682-689, 1993.
-
(1993)
Proceedings of the IEEE
, vol.81
, pp. 682-689
-
-
Hu, C.1
-
113
-
-
84892285310
-
IEEE P1005 draft standard for definitions, symbols, and characteristics of floating gate memory arrays
-
approved
-
IEEE Standard Department, "IEEE P1005 draft standard for definitions, symbols, and characteristics of floating gate memory arrays", approved 1998.
-
(1998)
IEEE Standard Department
-
-
-
114
-
-
0034995124
-
New technique for fast characterisation of SILC distribution in flash arrays
-
D. Ielmini, A.S. Spinelli, A.L. Lacaita, L. Confalonieri, A. Visconti, "New technique for Fast Characterisation of SILC Distribution in Flash Arrays", Proc. IRPS, pp. 73-80, 2001.
-
(2001)
Proc. IRPS
, pp. 73-80
-
-
Ielmini, D.1
Spinelli, A.S.2
Lacaita, A.L.3
Confalonieri, L.4
Visconti, A.5
-
115
-
-
0036087158
-
Localisation of SILC in flash memories after program/erase cycling
-
D. Ielmini, A.S. Spinelli, A.L. Lacaita, R. Leone, A. Visconti, "Localisation of SILC in Flash Memories after Program/Erase Cycling", Proc. IRPS, pp. 1-6, 2002.
-
(2002)
Proc. IRPS
, pp. 1-6
-
-
Ielmini, D.1
Spinelli, A.S.2
Lacaita, A.L.3
Leone, R.4
Visconti, A.5
-
116
-
-
0035716243
-
Statistical model of reliability and scaling projections for flash memories
-
D. Ielmini, A. Spinelli, A. Lacaita, A. Modelli, "Statistical Model of Reliability and Scaling Projections for Flash Memories", IEDM Tech. Dig., 2001.
-
(2001)
IEDM Tech. Dig
-
-
Ielmini, D.1
Spinelli, A.2
Lacaita, A.3
Modelli, A.4
-
117
-
-
0030081176
-
A 3.3-V 128-Mb multilevel NAND flash memory for mass storage applications
-
February
-
T. S. Jung et al., "A 3.3-V 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications", in ISSCC Dig. Tech. Papers, pp. 32-33, February 1996.
-
(1996)
ISSCC Dig. Tech. Papers
, pp. 32-33
-
-
Jung, T.S.1
-
118
-
-
20244380154
-
Bit-line clamped sensing multiplex and accurate high-voltage generator for 0.25 μM flash memories
-
February
-
T. Kawahara et al., "Bit-Line Clamped Sensing Multiplex and Accurate High-Voltage Generator for 0.25 μM Flash Memories", in 1996 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., pp. 38-39, February 1996.
-
(1996)
1996 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap
, pp. 38-39
-
-
Kawahara, T.1
-
119
-
-
0035716640
-
A 130 nm generation high-density ETOX flash memory technology
-
S. Keeney, "A 130 nm Generation High-Density ETOX Flash Memory Technology", IEDM Tech. Dig., p. 41, 2001.
-
(2001)
IEDM Tech. Dig
, pp. 41
-
-
Keeney, S.1
-
120
-
-
0026972636
-
Complete transient simulation of flash EEPROM devices
-
S. Kenney et al., "Complete Transient Simulation of Flash EEPROM Devices", IEEE Transaction on Electron Devices, Vol. 39, pp. 2750-2757, 1992.
-
(1992)
IEEE Transaction on Electron Devices
, vol.39
, pp. 2750-2757
-
-
Kenney, S.1
-
121
-
-
0034876893
-
Low output resistance charge pump for flash memory programming
-
San Jose, CA (USA), August
-
O. Khouri, S. Gregori, R. Micheloni, D. Soltesz, G. Torelli, "Low Output Resistance Charge Pump for Flash Memory Programming", 2001 IEEE Proc. Int. Workshop on Memory Technology, Design and Testing, San Jose, CA (USA), pp. 99-104, August 2001.
-
(2001)
2001 IEEE Proc. Int. Workshop on Memory Technology, Design and Testing
, pp. 99-104
-
-
Khouri, O.1
Gregori, S.2
Micheloni, R.3
Soltesz, D.4
Torelli, G.5
-
122
-
-
84902317767
-
Improved charge pump for flash memory applications in triple-well CMOS technology
-
L'Aquila (Italy), July
-
O. Khouri, S. Gregori, A. Cabrini, R. Micheloni, G. Torelli, "Improved Charge Pump for Flash Memory Applications in Triple-Well CMOS Technology", in 2002 IEEE Proc. Int. Symposium on Industrial Electronics, L'Aquila (Italy), pp. 1322-1326, July 2002.
-
(2002)
2002 IEEE Proc. Int. Symposium on Industrial Electronics
, pp. 1322-1326
-
-
Khouri, O.1
Gregori, S.2
Cabrini, A.3
Micheloni, R.4
Torelli, G.5
-
123
-
-
0033684568
-
Fast voltage regulator for multilevel flash memories
-
August
-
O. Khouri, R. Micheloni, S. Gregori, G. Torelli, "Fast Voltage Regulator for Multilevel Flash Memories", in Records 2000 IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 34-38, August 2000.
-
(2000)
Records 2000 IEEE Int. Workshop on Memory Technology, Design and Testing
, pp. 34-38
-
-
Khouri, O.1
Micheloni, R.2
Gregori, S.3
Torelli, G.4
-
124
-
-
84891388780
-
-
U.S. Patent No. 6.259.635
-
O. Khouri, R. Micheloni, I. Motta, A. Sacco, G. Torelli, "Capacitive Boosting Circuit for the Regulation of the Word Line Reading Voltage in Non-Volatile Memories", U.S. Patent No. 6.259.635.
-
Capacitive Boosting Circuit for the Regulation of the Word Line Reading Voltage in Non-Volatile Memories
-
-
Khouri, O.1
Micheloni, R.2
Motta, I.3
Sacco, A.4
Torelli, G.5
-
125
-
-
33646853350
-
Word-line read voltage regulator with capacitive boosting for multimegabit multilevel flash memories
-
August-September
-
O. Khouri, R. Micheloni, I. Motta, G. Torelli, "Word-Line Read Voltage Regulator with Capacitive Boosting for Multimegabit Multilevel Flash Memories", in Proc. European Conf. Circuit Theory and Design 1999, Vol. I, pp. 145-148, August-September 1999.
-
(1999)
Proc. European Conf. Circuit Theory and Design 1999
, vol.1
, pp. 145-148
-
-
Khouri, O.1
Micheloni, R.2
Motta, I.3
Torelli, G.4
-
126
-
-
33646852105
-
Program word-line voltage generator for multilevel flash memories
-
December
-
O. Khouri, R. Micheloni, A. Sacco, G. Campardo, G. Torelli, "Program Word-Line Voltage Generator for Multilevel Flash Memories", in Proc. 7th IEEE Int. Conf. on Electronics, Circuits, and Systems, Vol. II, pp. 1030-1033, December 2000.
-
(2000)
Proc. 7th IEEE Int. Conf. on Electronics, Circuits, and Systems
, vol.2
, pp. 1030-1033
-
-
Khouri, O.1
Micheloni, R.2
Sacco, A.3
Campardo, G.4
Torelli, G.5
-
127
-
-
0002510626
-
Very fast recovery word-line voltage regulator for multilevel non-volatile memories
-
Athens, Greece, June
-
O. Khouri, R. Micheloni, G. Torelli, "Very Fast Recovery Word-Line Voltage Regulator for Multilevel Non-volatile Memories", in Proc. Third IMACS/IEEE Int. Multiconference Circuits, Communications and Computers, Athens, Greece, pp. 3781-3784, June 1999.
-
(1999)
Proc. Third IMACS/IEEE Int. Multiconference Circuits, Communications and Computers
, pp. 3781-3784
-
-
Khouri, O.1
Micheloni, R.2
Torelli, G.3
-
128
-
-
0024612454
-
Analysis of coupling noise between adjacent bit lines in megabit DRAM's
-
February
-
Y. Konishi et al., "Analysis of Coupling Noise Between Adjacent Bit Lines in Megabit DRAM's", IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, February 1989.
-
(1989)
IEEE Journal of Solid-State Circuits
, vol.24
, Issue.1
-
-
Konishi, Y.1
-
129
-
-
0024132428
-
An In-System reprogrammable 256 K CMOS flash memory
-
V. N. Kynett et al., "An In-System Reprogrammable 256 K CMOS Flash Memory", ISSCC, Conf. Proc., pp. 132-133, 1988.
-
(1988)
ISSCC, Conf. Proc.
, pp. 132-133
-
-
Kynett, V.N.1
-
130
-
-
0024752312
-
A 90-ns one-million erase/program cycle 1-mbit flash memory
-
October
-
V. N. Kynett et al., "A 90-ns one-million Erase/Program Cycle 1-Mbit Flash memory", IEEE Journal of Solid-State Circuits, Vol. SC-24, pp. 1259-1264, October 1989.
-
(1989)
IEEE Journal of Solid-State Circuits
, vol.SC-24
, pp. 1259-1264
-
-
Kynett, V.N.1
-
131
-
-
84858872734
-
Fowler-Nordheim tunnelling into thermally grown SiO2
-
M. Lenzlinger, E. H. Show, "Fowler-Nordheim Tunnelling into Thermally Grown SiO2", IEDM Technical Digest, Vol. 40, pp. 273-283, 1969.
-
(1969)
IEDM Technical Digest
, vol.40
, pp. 273-283
-
-
Lenzlinger, M.1
Show, E.H.2
-
132
-
-
0030784211
-
Program load adaptive voltage regulator for flash memories
-
January
-
M. MacCarrone et al., "Program Load Adaptive Voltage Regulator for Flash Memories", Journal of Solid-State Circuit, Vol. 32, No. 1, p. 100, January 1997.
-
(1997)
Journal of Solid-State Circuit
, vol.32
, Issue.1
, pp. 100
-
-
MacCarrone, M.1
-
133
-
-
0036638639
-
CHISEL flash EEPROM-Part I: Performance and scaling
-
July
-
S. Mahapatra, S. Shukuri, J. Bude, "CHISEL Flash EEPROM-Part I: Performance and Scaling", IEEE Trans. Electron Devices, Vol. ED-49, pp. 1296-1301, July 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.ED-49
, pp. 1296-1301
-
-
Mahapatra, S.1
Shukuri, S.2
Bude, J.3
-
135
-
-
0020833206
-
Circuit techniques for a VLSI memory
-
October
-
T. Mano, J. Yamada, J. Inoue, and S. Nakajima, "Circuit Techniques for a VLSI Memory", IEEE Journal of Solid-State Circuits, Vol. 18, No. 5, pp. 463-469, October 1983.
-
(1983)
IEEE Journal of Solid-State Circuits
, vol.18
, Issue.5
, pp. 463-469
-
-
Mano, T.1
Yamada, J.2
Inoue, J.3
Nakajima, S.4
-
136
-
-
0028735413
-
The solution of over-erase problem controlling poly-Si grain size- Modified scaling principles for flash memory
-
S. Maramatsu et al., "The solution of Over-Erase Problem Controlling Poly-Si Grain Size- Modified Scaling Principles for Flash Memory", IEDM Tech. Dig., pp. 847-850, 1994.
-
(1994)
IEDM Tech. Dig
, pp. 847-850
-
-
Maramatsu, S.1
-
137
-
-
0026136675
-
An experimental 4-Mb flash EEPROM with sector erase
-
April
-
M. McConnel et al., "An Experimental 4-Mb Flash EEPROM with Sector Erase", IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, pp. 484-489, April 1991.
-
(1991)
IEEE Journal of Solid-State Circuits
, vol.26
, Issue.4
, pp. 484-489
-
-
McConnel, M.1
-
144
-
-
0033697934
-
Hierarchical sector biasing organization for flash memories
-
August
-
R. Micheloni, M. Zammattio, G. Campardo, O. Khouri, G. Torelli, "Hierarchical Sector Biasing Organization for Flash Memories", in Records 2000 IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 29-33, August 2000.
-
(2000)
Records 2000 IEEE Int. Workshop on Memory Technology, Design and Testing
, pp. 29-33
-
-
Micheloni, R.1
Zammattio, M.2
Campardo, G.3
Khouri, O.4
Torelli, G.5
-
145
-
-
33646848974
-
Stand-by low-Power architecture in a 3-V only 2-bit/cell 64-Mbit flash memory
-
September
-
R. Micheloni, I. Motta, O. Khouri, G. Torelli, "Stand-by Low-Power Architecture in a 3-V only 2-bit/cell 64-Mbit Flash Memory", in Proc. 8th IEEE Int. Conf. Electronics, Circuits, and Systems, Vol. II, pp. 929-932, September 2001.
-
(2001)
Proc. 8th IEEE Int. Conf. Electronics, Circuits, and Systems
, vol.2
, pp. 929-932
-
-
Micheloni, R.1
Motta, I.2
Khouri, O.3
Torelli, G.4
-
146
-
-
33646848974
-
Stand-by low-Power architecture in a 3-V only 2-bit/cell 64-Mbit flash memory
-
September
-
R. Micheloni, I. Motta, O. Khouri, G. Torelli, "Stand-by Low-Power Architecture in a 3-V only 2-bit/cell 64-Mbit Flash Memory", in Proc. 8th IEEE Int. Conf. Electronics, Circuits, and Systems, Vol. II, pp. 929-932, September 2001.
-
(2001)
Proc. 8th IEEE Int. Conf. Electronics, Circuits, and Systems
, vol.2
, pp. 929-932
-
-
Micheloni, R.1
Motta, I.2
Khouri, O.3
Torelli, G.4
-
147
-
-
33646847344
-
A 0.13-μm CMOS nor flash memory experimental chip for 4-b/cell storage
-
September
-
R. Micheloni et al., "A 0.13-μm CMOS NOR Flash Memory Experimental Chip for 4-b/cell Storage", ESSCIRC 28th Proc. European Solid-State Circuit Conf., pp. 131-134, September 2002.
-
(2002)
ESSCIRC 28th Proc. European Solid-State Circuit Conf
, pp. 131-134
-
-
Micheloni, R.1
-
148
-
-
13444275716
-
The flash memory read path building blocks and critical aspects
-
April
-
R. Micheloni et al., "The Flash Memory Read Path Building Blocks and Critical Aspects", IEEE Proceeding of the, Vol. 91, No. 4, pp. 537-553, April 2003.
-
(2003)
IEEE Proceeding of the
, vol.91
, Issue.4
, pp. 537-553
-
-
Micheloni, R.1
-
149
-
-
0029701394
-
Negative heap pump for low voltage operation flash memory
-
June
-
M. Mihara, Y. Terada, M. Yamada, "Negative Heap Pump for Low Voltage Operation Flash Memory", in 1996 Symposium VLSI Circuits Dig. Tech. Pap., pp. 76-77, June 1996.
-
(1996)
1996 Symposium VLSI Circuits Dig. Tech. Pap
, pp. 76-77
-
-
Mihara, M.1
Terada, Y.2
Yamada, M.3
-
150
-
-
0031121346
-
Area-Efficient layout design for CMOS output transistors
-
April
-
K. Ming-Dou, W. Chung-Yu, W. Tain-Shun, "Area-Efficient Layout Design for CMOS Output Transistors", IEEE, Trans. On Electron Devices, Vol. 44, No. 4, April 1997.
-
(1997)
IEEE, Trans. on Electron Devices
, vol.44
, Issue.4
-
-
Ming-Dou, K.1
Chung-Yu, W.2
Tain-Shun, W.3
-
151
-
-
0026853679
-
A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories
-
April
-
Y. Miyawaki et al., "A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16-Mb/64-Mb Flash Memories", IEEE Journal of Solid State Circuits, Vol. 27, No. 4, April 1992.
-
(1992)
IEEE Journal of Solid State Circuits
, vol.27
, Issue.4
-
-
Miyawaki, Y.1
-
152
-
-
84891472956
-
Read-Disturb failure in flash memory at low field
-
Nikkei Electronics Asia, May
-
Y. Mochizucki, "Read-Disturb Failure in Flash Memory at Low Field", Intel reports, Nikkei Electronics Asia, pp. 35-36, May 1993.
-
(1993)
Intel Reports
, pp. 35-36
-
-
Mochizucki, Y.1
-
153
-
-
33646834478
-
Multi-level flash memory technology
-
Tokyo, Extended Abstract
-
A. Modelli, R. Bez, A.Visconti "Multi-level Flash Memory Technology", 2001 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Extended Abstract, pp. 516-517, 2001.
-
(2001)
2001 International Conference on Solid State Devices and Materials (SSDM)
, pp. 516-517
-
-
Modelli, A.1
Bez, R.2
Visconti, A.3
-
154
-
-
0035445243
-
Basic feasibility constraints for multilevel CHE programmed flash memories
-
September
-
A. Modelli, A. Manstretta, G. Torelli, "Basic Feasibility Constraints for Multilevel CHEProgrammed Flash Memories", IEEE Transaction Electron Devices, Vol. ED-48, pp. 2032-2042, September 2001.
-
(2001)
IEEE Transaction Electron Devices
, vol.ED-48
, pp. 2032-2042
-
-
Modelli, A.1
Manstretta, A.2
Torelli, G.3
-
155
-
-
0026107524
-
ONO interpoly dielectric scaling for Non-volatile memories applications
-
S. Mori et al., "ONO Interpoly Dielectric Scaling for Non-Volatile Memories Applications", IEEE Trans. On Electron Devices, Vol. 38, No. 2, pp. 386-391, 1991.
-
(1991)
IEEE Trans. on Electron Devices
, vol.38
, Issue.2
, pp. 386-391
-
-
Mori, S.1
-
156
-
-
0032138640
-
A Step-down boosted-wordline scheme for 1-V battery-Operated fast SRAM's
-
August
-
H. Morimura, N. Shibata, "A Step-Down Boosted-Wordline Scheme for 1-V Battery-Operated Fast SRAM's", IEEE Journal of Solid-State Circuits, Vol. SC-33, No. 8, August 1998.
-
(1998)
IEEE Journal of Solid-State Circuits
, vol.SC-33
, Issue.8
-
-
Morimura, H.1
Shibata, N.2
-
157
-
-
33646836459
-
High-voltage management in single-supply CHE nor-type flash memories
-
I. Motta, G. Ragone, O. Khouri, G. Torelli, R. Micheloni, "High-Voltage Management in Single-Supply CHE NOR-Type Flash Memories", Proceedings of the IEEE, Vol. 91, pp. 554-568, 2003.
-
(2003)
Proceedings of the IEEE
, vol.91
, pp. 554-568
-
-
Motta, I.1
Ragone, G.2
Khouri, O.3
Torelli, G.4
Micheloni, R.5
-
158
-
-
0022290451
-
A Single transistor EEPROM cell and its implementation in a 512 K CMOS EEPROM
-
S. Mukherjee, T. Chang, R. Pang, M. Knecht, D. Hu, "A Single Transistor EEPROM Cell and its Implementation in a 512 K CMOS EEPROM", IEDM Tech. Dig., pp. 616-619, 1958.
-
(1958)
IEDM Tech. Dig
, pp. 616-619
-
-
Mukherjee, S.1
Chang, T.2
Pang, R.3
Knecht, M.4
Hu, D.5
-
159
-
-
0022700963
-
Sensitivity of dynamic MOS Flip-Flop sense amplifiers
-
April
-
K. Natori, "Sensitivity of dynamic MOS Flip-Flop Sense Amplifiers", IEEE Transaction on Electron Devices, Vol. ED-33, No. 4, pp. 482-488, April 1986.
-
(1986)
IEEE Transaction on Electron Devices
, vol.ED-33
, Issue.4
, pp. 482-488
-
-
Natori, K.1
-
160
-
-
0030288232
-
A 9.8 mm 2 Die size 3.3 V 64 Mb flash memory with FN-nor type four level cell
-
November 96
-
M. Ohkawa el al., "A 9.8 mm 2 Die size 3.3 V 64 Mb Flash Memory with FN-NOR type Four Level Cell", IEEE Journal of Solid-State Circuit, Vol. 31, No. 11, p. 1584, November 96.
-
IEEE Journal of Solid-State Circuit
, vol.31
, Issue.11
, pp. 1584
-
-
Al, M.O.E.1
-
161
-
-
0031210025
-
Circuit Techniques for 1.5-V Power Supply Flash Memory
-
August
-
N. Otsuka, M. A. Horowitz, "Circuit Techniques for 1.5-V Power Supply Flash Memory", IEEE Journal of Solid-State Circuits, Vol. 32, No. 8, August 1997.
-
(1997)
IEEE Journal of Solid-State Circuits
, vol.32
, Issue.8
-
-
Otsuka, N.1
Horowitz, M.A.2
-
162
-
-
0031212918
-
Flash memory Cells - An overview
-
P. Pavan, R. Bez, P. Olivo, E. Zanoni, "Flash Memory Cells - An Overview", Proceedings of the IEEE, Vol. 85, pp. 1248-1271, 1997.
-
(1997)
Proceedings of the IEEE
, vol.85
, pp. 1248-1271
-
-
Pavan, P.1
Bez, R.2
Olivo, P.3
Zanoni, E.4
-
163
-
-
4344597192
-
High-Speed Low-Power sense comparator for multilevel flash memories
-
December
-
A. Pierin, S. Gregori, O. Khouri, R. Micheloni, G. Torelli, "High-Speed Low-Power Sense Comparator for Multilevel Flash Memories" in Proc. 7th Int. Conf. Electronics, Circuits and Systems, Vol. II, pp. 759-762, December 2000.
-
(2000)
Proc. 7th Int. Conf. Electronics, Circuits and Systems
, vol.2
, pp. 759-762
-
-
Pierin, A.1
Gregori, S.2
Khouri, O.3
Micheloni, R.4
Torelli, G.5
-
165
-
-
0021622790
-
Design techniques for Cascode CMOS Op amps with Im-proved PSRR and common mode input range
-
December
-
D. B. Ribner, M. A. Copeland, Design Techniques for Cascode CMOS Op Amps with Im-proved PSRR and Common Mode Input Range, IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 6, pp. 919-925, December 1984.
-
(1984)
IEEE Journal of Solid-State Circuits
, vol.SC-19
, Issue.6
, pp. 919-925
-
-
Ribner, D.B.1
Copeland, M.A.2
-
166
-
-
0032304222
-
Nonvolatile multilevel memories for digital applications
-
December
-
B. Riccò et al., "Nonvolatile Multilevel Memories for Digital Applications", Proc. IEEE, Vol. 86, pp. 2399-2421, December 1998.
-
(1998)
Proc. IEEE
, vol.86
, pp. 2399-2421
-
-
Riccò, B.1
-
167
-
-
0031698077
-
A Low-Voltage, low quiescent current, low Drop-out regulator
-
January
-
G. A. Rincon-Mora, P. E. Allen, "A Low-Voltage, Low Quiescent Current, Low Drop-out Regulator", IEEE Journal of Solid-State Circuits, Vol. SC-33, pp. 36-44, January 1998.
-
(1998)
IEEE Journal of Solid-State Circuits
, vol.SC-33
, pp. 36-44
-
-
Rincon-Mora, G.A.1
Allen, P.E.2
-
168
-
-
0005209142
-
A 32 Mb-4b/cell analog flash memory supporting variable density with only supply and serial I/O
-
P. L. Rolandi et al., "A 32 Mb-4b/cell Analog Flash Memory Supporting Variable Density with Only Supply and serial I/O", 25th ESSCIRC '99.
-
25th ESSCIRC '99
-
-
Rolandi, P.L.1
-
169
-
-
0031703348
-
1M-cell 6b/cell analog Ffash memory for digital storage
-
February
-
P. L. Rolandi et al., "1M-cell 6b/cell Analog Flash Memory for Digital Storage", IEEE ISSCC Dig. Tech. Papers, pp. 334-335, February 1998.
-
(1998)
IEEE ISSCC Dig. Tech. Papers
, pp. 334-335
-
-
Rolandi, P.L.1
-
170
-
-
0020704286
-
Single formulas for two-and three-dimensional capacitances
-
February
-
T. Sakurai, K. Tamaru, "Single Formulas for Two-and Three-Dimensional Capacitances", IEEE Transactions on Electron Devices, Vol. ED-30, No. 2, pp. 183-185, February 1983.
-
(1983)
IEEE Transactions on Electron Devices
, vol.ED-30
, Issue.2
, pp. 183-185
-
-
Sakurai, T.1
Tamaru, K.2
-
171
-
-
0002906607
-
Physical aspects of cell operation and reliability
-
P. Cappelletti et al. Ed Norwell, Ma: Kluwer
-
L. Selmi, C. Fiegna, "Physical Aspects of Cell Operation And Reliability", in Flash Memory, P. Cappelletti et al., Ed Norwell, Ma: Kluwer, 1999.
-
(1999)
Flash Memory
-
-
Selmi, L.1
Fiegna, C.2
-
172
-
-
20444504862
-
Modular architecture for a family of multilevel 256/192/128/64Mb 2-Bit/Cell 3V only NOR flash memory devices
-
Malta, September
-
A. Silvagni et al., "Modular Architecture For a Family of Multilevel 256/192/128/64Mb 2-Bit/Cell 3V Only NOR FLASH Memory Devices", ICECS 2001, Malta, September 2001.
-
(2001)
ICECS 2001
-
-
Silvagni, A.1
-
174
-
-
0030284603
-
Different dependence of band-to-band and fowler-nordheim tunneling on source doping concentration of an n-MOSFET
-
Y. Tang et al., "Different Dependence of Band-to-Band and Fowler-Nordheim Tunneling on Source Doping Concentration of an n-MOSFET", IEEE Electron Device Letters, Vol. 17, p. 525, 1996.
-
(1996)
IEEE Electron Device Letters
, vol.17
, pp. 525
-
-
Tang, Y.1
-
175
-
-
0033169552
-
Optimization of Word-Line booster circuits for Low-Voltage flash memories
-
August
-
T. Tanzawa, S. Atsumi, "Optimization of Word-Line Booster Circuits for Low-Voltage Flash Memories", IEEE Journal of Solid-State Circuits, Vol. SC-34, pp. 1091-1098, August 1999.
-
(1999)
IEEE Journal of Solid-State Circuits
, vol.SC-34
, pp. 1091-1098
-
-
Tanzawa, T.1
Atsumi, S.2
-
176
-
-
0031210141
-
A dynamic analysis of the dickson charge pump circuit
-
August
-
T. Tanzawa, T. Tanaka, "A Dynamic Analysis of the Dickson Charge Pump Circuit", IEEE Journal of Solid-State Circuits, Vol. SC-32, No. 8, pp. 1231-1240, August 1997.
-
(1997)
IEEE Journal of Solid-State Circuits
, vol.SC-32
, Issue.8
, pp. 1231-1240
-
-
Tanzawa, T.1
Tanaka, T.2
-
178
-
-
0026953337
-
A 5 V-only operation 0.6-um flash EEPROM with row decoder scheme in Triple-Well structure
-
A. Umezawa et al., (1992), "A 5 V-only Operation 0.6-um Flash EEPROM with Row Decoder Scheme in Triple-Well Structure", IEEE Journal of Solid-State Circuits, Vol. 27, pp. 1540-1546.
-
(1992)
IEEE Journal of Solid-State Circuits
, vol.27
, pp. 1540-1546
-
-
Umezawa, A.1
-
179
-
-
0018516346
-
On the I-V characteristics of Floating-Gate mos transistors
-
September
-
S. T. Wang, "On the I-V Characteristics of Floating-Gate Mos Transistors", IEEE Transaction on Electron Devices, Vol. ED-26, No. 9, September 1979.
-
(1979)
IEEE Transaction on Electron Devices
, vol.ED-26
, Issue.9
-
-
Wang, S.T.1
-
180
-
-
0031166547
-
Efficiency improvement in charge pump circuits
-
June
-
C. C. Wang, J. Wu, "Efficiency Improvement in Charge Pump Circuits", IEEE Journal of Solid-State Circuits, Vol. SC-32, pp. 852-860, June 1997.
-
(1997)
IEEE Journal of Solid-State Circuits
, vol.SC-32
, pp. 852-860
-
-
Wang, C.C.1
Wu, J.2
-
182
-
-
0035942669
-
Improved voltage tripler structure with symmetrical stacking charge pump
-
May
-
M. Zhang. N. Llaser, F. Devos, "Improved Voltage Tripler Structure with Symmetrical Stacking Charge Pump", Electronics Letters, Vol. 37, pp. 668-669, May 2001.
-
(2001)
Electronics Letters
, vol.37
, pp. 668-669
-
-
Llaser, M.Zhang.N.1
Devos, F.2
-
183
-
-
28144453513
-
An 8Gb Multi-level NAND flash memory with 63 nm STI CMOS process technology
-
D. S. Byeon et al, "An 8Gb Multi-level NAND Flash Memory with 63 nm STI CMOS Process technology", ISSCC 2005 Digest of Technical Papers, pp. 46-47.
-
ISSCC 2005 Digest of Technical Papers
, pp. 46-47
-
-
Byeon, D.S.1
-
184
-
-
0035054744
-
A 3.3 V 1 Gb Multi-level nand flash memory with Non-uniform threshold voltage distribution
-
T. Cho et al., "A 3.3 V 1 Gb Multi-level NAND Flash Memory with Non-uniform Threshold Voltage Distribution", ISSCC 2001 Digest of Technical Papers, pp. 28-29.
-
ISSCC 2001 Digest of Technical Papers
, pp. 28-29
-
-
Cho, T.1
-
185
-
-
0029707030
-
A high speed programming scheme for Multi-Level NAND flash memory
-
June
-
Y.-J. Choi, K.-D. Suh, Y.-N. Koh, J.-W. Park, K.-J. Lee, Y.-J. Cho, B.-H. Suh, "A High Speed Programming Scheme for Multi-Level NAND Flash Memory", in 1996 Symposium VLSI Circuits Dig. Tech. Papers., pp. 170-171, June 1996.
-
(1996)
1996 Symposium VLSI Circuits Dig. Tech. Papers
, pp. 170-171
-
-
Choi, Y.-J.1
Suh, K.-D.2
Koh, Y.-N.3
Park, J.-W.4
Lee, K.-J.5
Cho, Y.-J.6
Suh, B.-H.7
-
186
-
-
0035506993
-
A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-MB single-level modes
-
November
-
T. Cho, Y.-T. Lee, E.-C. Kim, J.-W. Lee, S. Choi, S. Lee, D.-H. Kim, W.-G. Han, Y.-H. Lim, J.-D. Lee, J.-D. Choi, and K.-D. Suh. "A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes, " IEEE Journal of, Vol. 26, No. 11, pp. 1700-1706, November 2001.
-
(2001)
IEEE Journal of
, vol.26
, Issue.11
, pp. 1700-1706
-
-
Cho, T.1
Lee, Y.-T.2
Kim, E.-C.3
Lee, J.-W.4
Choi, S.5
Lee, S.6
Kim, D.-H.7
Han, W.-G.8
Lim, Y.-H.9
Lee, J.-D.10
Choi, J.-D.11
Suh, K.-D.12
-
187
-
-
0031699487
-
A new write/erase method to improve the read disturb characteristics based on the decay phenomena of stress leakage current for flash memories
-
January
-
T. Endoh et al., "A New Write/Erase Method to Improve the Read Disturb Characteristics Based on the Decay Phenomena of Stress Leakage Current for Flash Memories", IEEE Transactions on Electron Devices, Vol. 45, No. 1, pp. 98-104, January 1998.
-
(1998)
IEEE Transactions on Electron Devices
, vol.45
, Issue.1
, pp. 98-104
-
-
Endoh, T.1
-
188
-
-
28144459824
-
A 146mm/sup 2/8 Gb nand flash memory with 70 nm CMOS technology
-
T. Hara et al, "A 146mm/sup 2/8 Gb NAND Flash Memory with 70 nm CMOS Technology", ISSCC 2005 Digest of Technical Papers, pp. 44-45.
-
ISSCC 2005 Digest of Technical Papers
, pp. 44-45
-
-
Hara, T.1
-
189
-
-
0029480949
-
Fast and accurate Pro-gramming method for Multi-level NAND EEPROMs
-
June
-
G. J. Hemink, T. Tanaka, T. Endoh, S. Aritome, R. Shirota, "Fast and Accurate Pro-gramming Method for Multi-Level NAND EEPROMs", in 1995 Symposium VLSI Technology Dig. Tech. Papers., pp. 129-130, June 1995.
-
(1995)
1995 Symposium VLSI Technology Dig. Tech. Papers
, pp. 129-130
-
-
Hemink, G.J.1
Tanaka, T.2
Endoh, T.3
Aritome, S.4
Shirota, R.5
-
190
-
-
84892320293
-
A high speed failure bit counter for the Pseudo Pass Scheme (PPS) in program operation for giga bit NAND flash
-
K. Hosono et al., "A High Speed Failure Bit Counter for the Pseudo Pass Scheme (PPS) in Program Operation for Giga Bit NAND Flash", NVMWS 2004.
-
NVMWS 2004
-
-
Hosono, K.1
-
191
-
-
0002124792
-
A 130 mm2 256 Mb nand flash with shallow trench isolation technology
-
K. Inamiya et al., "A 130 mm2 256 Mb NAND flash with shallow trench isolation technology", ISSCC 1999 Digest of Technical Papers, pp. 112-113.
-
ISSCC 1999 Digest of Technical Papers
, pp. 112-113
-
-
Inamiya, K.1
-
192
-
-
0030291637
-
A 117-mm2 3.3 V only 128-Mb multilevel NAND flash memory for mass storage applications
-
November
-
T. S. Jung, Y.-J. Choi, K.-D. Suh, B.-H. Suh, J.-K. Kim, Y.-H. Lim, Y.-N. Koh, J.-W. Park, K.-J. Lee, J.-H. Park, K.-T. Park, J.-R. Kim, J.-H. Lee, H.-K. Lim, "A 117-mm2 3.3 V only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications", IEEE Journal of Solid-State Circuits, Vol. SC-31, pp. 1575-1583, November 1996.
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.SC-31
, pp. 1575-1583
-
-
Jung, T.S.1
Choi, Y.-J.2
Suh, K.-D.3
Suh, B.-H.4
Kim, J.-K.5
Lim, Y.-H.6
Koh, Y.-N.7
Park, J.-W.8
Lee, K.-J.9
Park, J.-H.10
Park, K.-T.11
Kim, J.-R.12
Lee, J.-H.13
Lim, H.-K.14
-
193
-
-
84892195957
-
Future outlook of nand flash technology for 40 nm node and beyond
-
K. Kim, "Future Outlook of NAND Flash Technology for 40 nm Node and Beyond", NVMWS 2004.
-
(2004)
NVMWS
-
-
Kim, K.1
-
194
-
-
0036575326
-
Effects of Floating-gate interference on nand flash memory cell operation
-
May
-
J. -D. Lee, "Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation", IEEE Electron Device Letters, Vol. 23, No. 5, pp. 264-266, May 2002.
-
(2002)
IEEE Electron Device Letters
, vol.23
, Issue.5
, pp. 264-266
-
-
Lee, J.-D.1
-
195
-
-
2442700147
-
A 3.3 V 4 Gb Four-level NAND flash memory with 90 nm CMOS technology
-
S. Lee et al, "A 3.3 V 4 Gb Four-level NAND Flash Memory with 90 nm CMOS technology", ISSCC 2004 Digest of Technical Papers, pp. 52-53.
-
ISSCC 2004 Digest of Technical Papers
, pp. 52-53
-
-
Lee, S.1
-
196
-
-
0038306352
-
A 1.8 V 2 Gb NAND flash memory for mass storage applications
-
J. Lee et al, "A 1.8 V 2 Gb NAND flash memory for mass storage applications" ISSCC 2003 Digest of Technical Papers, pp. 290-494.
-
ISSCC 2003 Digest of Technical Papers
, pp. 290-494
-
-
Lee, J.1
-
197
-
-
0023563047
-
New ultra high density EPROM and flash with NAND structure cell
-
F. Masuoka, M. Momodomi, Y. Iwata and R. Shirota, "New Ultra High Density EPROM and Flash with NAND Structure Cell", IEDM Tech. Dig., pp. 552-555, 1987.
-
(1987)
IEDM Tech. Dig
, pp. 552-555
-
-
Masuoka, F.1
Momodomi, M.2
Iwata, Y.3
Shirota, R.4
-
198
-
-
39749172648
-
A 4Gb 2b/cell NAND flash memory with embedded 5b BCH ECC for 36MB/s system read throughput
-
San Francisco, February
-
R. Micheloni et al. "A 4Gb 2b/Cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput", ISSCC Dig. Tech. Papers, San Francisco, February 2006.
-
(2006)
ISSCC Dig. Tech. Papers
-
-
Micheloni, R.1
-
199
-
-
0000027444
-
A 144-Mb, Eight-level nand flash memory with optimized pulsewidth programming
-
May
-
H. Nobukata et al., "A 144-Mb, Eight-Level NAND Flash Memory with Optimized Pulsewidth Programming, " IEEE Journal of Solid-State Circuits, Vol. 35, No. 5, pp. 682-690, May 2000.
-
(2000)
IEEE Journal of Solid-State Circuits
, vol.35
, Issue.5
, pp. 682-690
-
-
Nobukata, H.1
-
201
-
-
0029404872
-
A 3.3 V 32 Mb nand flash memory with incremental step pulse programming scheme
-
November
-
K. -D. Suh et al., "A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme, " IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, pp. 1149-1156, November 1995.
-
(1995)
IEEE Journal of Solid-State Circuits
, vol.30
, Issue.11
, pp. 1149-1156
-
-
Suh, K.-D.1
-
202
-
-
33846227684
-
A 56 nm CMOS 99 mm2 8 Gb Multi-level NAND flash memory with 10MB/s program throughput
-
K. Takeuchi et al., "A 56 nm CMOS 99 mm2 8 Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput" 2006 ISSCC Digest of Technical Papers, pp. 507-508.
-
2006 ISSCC Digest of Technical Papers
, pp. 507-508
-
-
Takeuchi, K.1
-
204
-
-
0032140032
-
A multipage cell architecture for High-Speed programming multilevel NAND flash memories
-
August
-
K. Takeuchi, T. Tanaka, T. Tanzawa, "A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories, " IEEE Journal of Solid-State Circuits, Vol. 33, No. 8, pp. 1228-1238, August 1998.
-
(1998)
IEEE Journal of Solid-State Circuits
, vol.33
, Issue.8
, pp. 1228-1238
-
-
Takeuchi, K.1
Tanaka, T.2
Tanzawa, T.3
-
205
-
-
0032625431
-
A negative vth cell architecture for highly scalable, excellent noise immune and high reliable NAND flash memories
-
May
-
K. Takeuchi et al., "A Negative Vth Cell Architecture for Highly Scalable, Excellent Noise Immune and High Reliable NAND Flash Memories, " IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 675-684, May 1999.
-
(1999)
IEEE Journal of Solid-State Circuits
, vol.34
, Issue.5
, pp. 675-684
-
-
Takeuchi, K.1
-
206
-
-
0034179167
-
A source-line programming scheme for low-voltage operation nand flash memories
-
May
-
K. Takeuchi et al., "A Source-Line Programming Scheme for Low-Voltage Operation NAND Flash Memories, " IEEE Journal of Solid-State Circuits, Vol. 35, No. 5, pp. 672-681, May 2000.
-
(2000)
IEEE Journal of Solid-State Circuits
, vol.35
, Issue.5
, pp. 672-681
-
-
Takeuchi, K.1
-
207
-
-
0028538112
-
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3V-only NAND flash memory
-
November
-
T. Tanaka et al., "A quick intelligent page-programming architecture and a shielded bitline sensing method for 3V-only NAND flash memory", IEEE Journal of Solid-State Circuits, Vol. 29, No. 11, November 1994, pp. 1366-1373.
-
(1994)
IEEE Journal of Solid-State Circuits
, vol.29
, Issue.11
, pp. 1366-1373
-
-
Tanaka, T.1
-
208
-
-
0031344954
-
A 3.4-Mbyte/sec programming 3-level nand flash memory saving 40% die size per bit
-
June
-
T. Tanaka, T. Tanzawa, K. Takekuchi, "A 3.4-Mbyte/sec Programming 3-level NAND Flash Memory Saving 40% Die Size per Bit", in 1997 Symposium VLSI Circuits Dig. Tech. Papers., pp. 65-66, June 1997.
-
(1997)
1997 Symposium VLSI Circuits Dig. Tech. Papers
, pp. 65-66
-
-
Tanaka, T.1
Tanzawa, T.2
Takekuchi, K.3
-
209
-
-
0027591522
-
Reliability issues of flash memory cells
-
May
-
A. Aritome, R. Shirota, G. Hemink, T. Endoh, F. Masoka, "Reliability Issues of Flash Memory Cells", Proc. IEEE, Vol. 81, pp. 776-788, May 1993.
-
(1993)
Proc. IEEE
, vol.81
, pp. 776-788
-
-
Aritome, A.1
Shirota, R.2
Hemink, G.3
Endoh, T.4
Masoka, F.5
-
211
-
-
0027306901
-
Novel read disturb failure mechanism induced by flash cycling
-
A. Brand, K. Wu, S. Pan, D. Chin, "Novel Read Disturb Failure Mechanism Induced by FLASH Cycling", in International Reliability Physics Symposium pp. 127-132, 1993.
-
(1993)
International Reliability Physics Symposium
, pp. 127-132
-
-
Brand, A.1
Wu, K.2
Pan, S.3
Chin, D.4
-
212
-
-
33847356136
-
Nonvolatile semiconductor memory technology
-
Eds., New York
-
W. D. Brown, J. E. Brewer, Eds., Nonvolatile Semiconductor Memory Technology, New York: IEEE Press, 1998.
-
(1998)
IEEE Press
-
-
Brown, W.D.1
Brewer, J.E.2
-
213
-
-
0034316131
-
z 64-Mb 2-b/cell che nor flash memory
-
November
-
z 64-Mb 2-b/Cell CHE NOR Flash Memory", IEEE Journal of Solid State Circuits, Vol. 35, No. 11, pp. 1655-1667, November 2000.
-
(2000)
IEEE Journal of Solid State Circuits
, vol.35
, Issue.11
, pp. 1655-1667
-
-
Campardo, G.1
-
214
-
-
0028756726
-
Failure mechanisms of flash cell in program/erase cycling
-
P. Cappelletti, R. Bez, D. Cantarelli, L. Fratin, "Failure Mechanisms of Flash Cell in Program/Erase Cycling", in IEDM Tech. Dig., pp. 291-294, 1994.
-
(1994)
IEDM Tech. Dig
, pp. 291-294
-
-
Cappelletti, P.1
Bez, R.2
Cantarelli, D.3
Fratin, L.4
-
215
-
-
84892314985
-
-
Eds., Boston, MA: Kluwer, Ch. 5
-
P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, Eds., "Flash Memories", Boston, MA: Kluwer, 1999, Ch. 5.
-
(1999)
Flash Memories
-
-
Cappelletti, P.1
Golla, C.2
Olivo, P.3
Zanoni, E.4
-
216
-
-
0029519228
-
Short channel enhanced degradation during discharge of flash eeprom memory cell
-
J. Chen, J. Hsu, S. Luan, Y. Tang, D. Liu, S. Haddad, C. Chang, S.
-
(1995)
IEDM Tech. Dig
, pp. 331-334
-
-
Chen, J.1
Hsu, J.2
Luan, S.3
Tang, Y.4
Liu, D.5
Haddad, S.6
Chang, C.7
Longcor, S.8
Lien, J.9
-
218
-
-
0037480823
-
Erratic erase in flash memories (part II): Dependence on operating conditions
-
A. Chimenton, P. Olivo, "Erratic Erase In Flash Memories (Part II): Dependence on Operating Conditions", IEEE Transaction on Electron Devices, Vol. 50, No. 4, pp. 1015-1021, 2003.
-
(2003)
IEEE Transaction on Electron Devices
, vol.50
, Issue.4
, pp. 1015-1021
-
-
Chimenton, A.1
Olivo, P.2
-
219
-
-
0037818414
-
Erratic erase in flash memories (part I): basic experimental and statistical characterization
-
A. Chimenton, P. Olivo, "Erratic Erase in Flash Memories (Part I): Basic Experimental and Statistical Characterization", in IEEE Transaction on Electron Devices, Vol. 50, No. 4, pp. 1009-1014, 2003.
-
(2003)
IEEE Transaction on Electron Devices
, vol.50
, Issue.4
, pp. 1009-1014
-
-
Chimenton, A.1
Olivo, P.2
-
220
-
-
70249113645
-
Reliability of Flash Memory Erasing Operation under High Tunneling Electric Field
-
A. Chimenton, P. Olivo, "Reliability of Flash Memory Erasing Operation under High Tunneling Electric Field", in Proc. IRPS, pp. 216-221, 2004.
-
(2004)
Proc. IRPS
, pp. 216-221
-
-
Chimenton, A.1
Olivo, P.2
-
221
-
-
20344367995
-
Reliability of erasing operation in nor-flash memories
-
July-August
-
A. Chimenton, P. Olivo, "Reliability of Erasing Operation in NOR-Flash Memories", introductory invited paper in Microelectronics Reliability, Vol. 45, No. 7-8, July-August, pp. 1094-1108, 2005.
-
(2005)
Introductory Invited Paper in Microelectronics Reliability
, vol.45
, Issue.7-8
, pp. 1094-1108
-
-
Chimenton, A.1
Olivo, P.2
-
223
-
-
0038545250
-
Analysis of erratic bits in flash memories
-
December
-
A. Chimenton, P. Pellati, P. Olivo, "Analysis of Erratic Bits in Flash Memories", IEEE Transactions on Devices and Materials Reliability, Vol. 1, pp. 179-184, December 2001.
-
(2001)
IEEE Transactions on Devices and Materials Reliability
, vol.1
, pp. 179-184
-
-
Chimenton, A.1
Pellati, P.2
Olivo, P.3
-
224
-
-
0036540521
-
Constant charge erasing scheme for flash memories
-
April
-
A. Chimenton, P. Pellati, P. Olivo, "Constant Charge Erasing Scheme for Flash Memories", IEEE Transactions on Electron Devices, Vol. 49, pp. 613-618, April 2002.
-
(2002)
IEEE Transactions on Electron Devices
, vol.49
, pp. 613-618
-
-
Chimenton, A.1
Pellati, P.2
Olivo, P.3
-
225
-
-
13244251813
-
Overerase phenomena: An insight into flash memory reliability
-
April
-
A. Chimenton, P. Pellati, P. Olivo, "Overerase Phenomena: An Insight Into Flash Memory Reliability, " in Proc. IEEE, Vol. 91, pp. 617-626, April 2003.
-
(2003)
Proc. IEEE
, vol.91
, pp. 617-626
-
-
Chimenton, A.1
Pellati, P.2
Olivo, P.3
-
226
-
-
0038348019
-
Erratic bits in flash memories under fowler- nordheim programming
-
A. Chimenton, P. Pellati, P. Olivo, "Erratic Bits in Flash Memories under Fowler- Nordheim Programming", Japanese Journal of Applied Physics, Vol. 42, No. 4B, pp. 2041-2043, 2003.
-
(2003)
Japanese Journal of Applied Physics
, vol.42
, Issue.4 B
, pp. 2041-2043
-
-
Chimenton, A.1
Pellati, P.2
Olivo, P.3
-
227
-
-
0036932374
-
Drain-accelerated degradation of tunnel oxides in flash memories
-
A. Chimenton, A. S. Spinelli, D. Ielmini, A. Lacaita, A. Visconti, P. Olivo, "Drain-accelerated Degradation of Tunnel Oxides in Flash Memories", in IEDM Tech. Dig., pp. 167-170, 2002.
-
(2002)
IEDM Tech. Dig.
, pp. 167-170
-
-
Chimenton, A.1
Spinelli, A.S.2
Ielmini, D.3
Lacaita, A.4
Visconti, A.5
Olivo, P.6
-
228
-
-
0028312527
-
Flash EPROM disturb mechanisms
-
C. Dunn, C. Kaya, T. Lewis, T. Strauss, J. Schreck, P. Hefley, M. Middendorf, T. San, "Flash EPROM Disturb Mechanisms", in Proc. IRPS, pp. 299-308, 1994.
-
(1994)
Proc. IRPS
, pp. 299-308
-
-
Dunn, C.1
Kaya, C.2
Lewis, T.3
Strauss, T.4
Schreck, J.5
Hefley, P.6
Middendorf, M.7
San, T.8
-
229
-
-
0026255223
-
Novel N2O-oxynitridation technology for forming highly reliable eeprom tunnel oxides films
-
H. Fukuda, M. Yasuda, T. Iwabuchi, S. Ohno, "Novel N2O-Oxynitridation Technology for Forming Highly Reliable EEPROM Tunnel Oxides Films", IEEE Electron Device Letters, Vol. 12, No. 11, pp. 587-589, 1991.
-
(1991)
IEEE Electron Device Letters
, vol.12
, Issue.11
, pp. 587-589
-
-
Fukuda, H.1
Yasuda, M.2
Iwabuchi, T.3
Ohno, S.4
-
230
-
-
4344701872
-
On-chip error correcting techniques for new-generation flash memories
-
April
-
S. Gregori, A. Cabrini, O. Khouri, G. Torelli, "On-Chip Error Correcting Techniques for New-Generation Flash Memories" Proc. IEEE, Vol. 91, No. 4, pp. 602-616, April 2003.
-
(2003)
Proc. IEEE
, vol.91
, Issue.4
, pp. 602-616
-
-
Gregori, S.1
Cabrini, A.2
Khouri, O.3
Torelli, G.4
-
231
-
-
0024627110
-
Degradations due to hole trapping in flash memory cells
-
S. Haddad, C. Chang, B. Swaminathan, J. Lien, "Degradations due to Hole Trapping in Flash Memory Cells", IEEE Electron Device Letters, Vol. 10, No. 3, pp. 117-119, 1989.
-
(1989)
IEEE Electron Device Letters
, vol.10
, Issue.3
, pp. 117-119
-
-
Haddad, S.1
Chang, C.2
Swaminathan, B.3
Lien, J.4
-
232
-
-
0028755689
-
Read- disturb degradation mechanism due to electron trapping in the tunnel oxide for low-voltage flash memories
-
M. Kato, N. Miyiamoto, H. Kume, A. Satoh, T. Adachi, M. Ushiyama, K. Rimura, "Read- Disturb Degradation Mechanism due to Electron Trapping in the Tunnel Oxide for Low-Voltage Flash Memories", in International Electron Device Meeting, pp. 45-48, 1994.
-
(1994)
International Electron Device Meeting
, pp. 45-48
-
-
Kato, M.1
Miyiamoto, N.2
Kume, H.3
Satoh, A.4
Adachi, T.5
Ushiyama, M.6
Rimura, K.7
-
234
-
-
0024752312
-
A 90-ns one-million erase/program cycle 1-mbit flash memory
-
V. N. Kynnet, M. L. Fandrich, J. Anderson, P. Dix, O. Jungroth, J. A. Kreifels, R. A. Lodenquai, B. Vajdic, S. Wells, M. D. Winston, L. Yang, "A 90-ns One-Million Erase/Program Cycle 1-Mbit Flash Memory" IEEE Journal of Solid-State Circuits, pp. 1259-1263, 1989.
-
(1989)
IEEE Journal of Solid-State Circuits
, pp. 1259-1263
-
-
Kynnet, V.N.1
Fandrich, M.L.2
Anderson, J.3
Dix, P.4
Jungroth, O.5
Kreifels, J.A.6
Lodenquai, R.A.7
Vajdic, B.8
Wells, S.9
Winston, M.D.10
Yang, L.11
-
236
-
-
0032646134
-
Using erase self-detrapped effect to eliminate the flash cell program/erase cycling vth window close
-
J. H. Lee, K. R. Peng, J. R. Shih, S. H. Chen, J. K. Yeh, H. D. Su, M. C. Ho, D. S. Kuo, B. K. Liew, Jack Y. C. Sun, "Using Erase Self-Detrapped Effect To Eliminate the Flash Cell Program/Erase Cycling Vth Window Close", in Proc. IRPS, pp. 24-29, 1999.
-
(1999)
Proc. IRPS
, pp. 24-29
-
-
Lee, J.H.1
Peng, K.R.2
Shih, J.R.3
Chen, S.H.4
Yeh, J.K.5
Su, H.D.6
Ho, M.C.7
Kuo, D.S.8
Liew, B.K.9
Sun, J.Y.C.10
-
237
-
-
11144248077
-
Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling
-
N. Mielke, H. Belgal, I. Kalastirsky, P. Kalavade, A. Kurtz, Q. Meng, N. Righos, J. Wu, "Flash EEPROM Threshold Instabilities due to Charge Trapping During Program/Erase Cycling", IEEE Transaction on Devices and Materials Reliability, Vol. 4, No. 3, pp. 335-344, 2004.
-
(2004)
IEEE Transaction on Devices and Materials Reliability
, vol.4
, Issue.3
, pp. 335-344
-
-
Mielke, N.1
Belgal, H.2
Kalastirsky, I.3
Kalavade, P.4
Kurtz, A.5
Meng, Q.6
Righos, N.7
Wu, J.8
-
238
-
-
4143148629
-
Advanced flash memory reliability
-
A. Modelli, A. Visconti, R. Bez, "Advanced Flash Memory Reliability", in IEEE International Conference on Integrated Circuit Design and Technology, pp. 211-218, 2004.
-
(2004)
IEEE International Conference on Integrated Circuit Design and Technology
, pp. 211-218
-
-
Modelli, A.1
Visconti, A.2
Bez, R.3
-
239
-
-
0028735413
-
The solution of over-erase problem controlling poly- si grain size -modified scaling principles for flash memory
-
S. Muramatsu, T. Kubota, N. Nishio, H. Shirai, M. Matsuo, N. Kodama, M. Horikawa, S. Saito, K. Arai, T. Okazawa, "The Solution of Over-Erase Problem Controlling Poly- Si Grain Size -Modified Scaling Principles for FLASH Memory-", in IEDM Tech. Dig., pp. 847-850, 1994.
-
(1994)
IEDM Tech. Dig
, pp. 847-850
-
-
Muramatsu, S.1
Kubota, T.2
Nishio, N.3
Shirai, H.4
Matsuo, M.5
Kodama, N.6
Horikawa, M.7
Saito, S.8
Arai, K.9
Okazawa, T.10
-
240
-
-
0024717906
-
A 5-V only one-transistor 256 k eeprom with page-mode erase
-
August
-
T. Nakayama, Y. Miyawaki, K. Kobayashi, Y. Terada, H. Arima, T. Matsukawa, T. Yoshihara, "A 5-V Only One-Transistor 256 K EEPROM with Page-Mode Erase", IEEE Journal of Solid-State Circuits, Vol. 24, pp. 911-915, August 1989.
-
(1989)
IEEE Journal of Solid-State Circuits
, vol.24
, pp. 911-915
-
-
Nakayama, T.1
Miyawaki, Y.2
Kobayashi, K.3
Terada, Y.4
Arima, H.5
Matsukawa, T.6
Yoshihara, T.7
-
241
-
-
0032686527
-
Effects of flash eeprom floating gate morphology on electrical behavior of fast programming bits
-
F. D. Nkansah, M. Hatalis, "Effects of Flash EEPROM Floating Gate Morphology on Electrical Behavior of Fast Programming Bits", IEEE Transaction on Electron Devices, Vol. 46, No. 7, pp. 1355-1362, 1999.
-
(1999)
IEEE Transaction on Electron Devices
, vol.46
, Issue.7
, pp. 1355-1362
-
-
Nkansah, F.D.1
Hatalis, M.2
-
242
-
-
0024125531
-
High field induced degradation in ultra-thin sio2 films
-
P. Olivo, T. Nguyen, B. Riccò, "High Field Induced Degradation in Ultra-Thin SiO2 Films" in IEEE Transactions on Electron Devices, Vol. 35, pp. 2259-2265, 1988.
-
(1988)
IEEE Transactions on Electron Devices
, vol.35
, pp. 2259-2265
-
-
Olivo, P.1
Nguyen, T.2
Riccò, B.3
-
243
-
-
84955615858
-
Erratic erase in etoxtm flash memory array
-
T. C. Ong, A. Fazio, N. Mielke, S. Pan, N. Righos, G. Atwood, S. Lai, "Erratic Erase in ETOXTM Flash Memory Array", in VLSI Symp. on Tech., pp. 83-84, 1993.
-
(1993)
VLSI Symp. on Tech
, pp. 83-84
-
-
Ong, T.C.1
Fazio, A.2
Mielke, N.3
Pan, S.4
Righos, N.5
Atwood, G.6
Lai, S.7
-
244
-
-
33747327940
-
A novel erasing technology for 3.3 v flash memory with 64 mb capacity and beyond
-
K. Oyama, H. Shirai, N. Kodama, K. Kanamori, K. Saitoh, Y.S. Hisamune, T.Okazawa, "A Novel Erasing Technology for 3.3 V Flash Memory with 64 Mb Capacity and Beyond", in IEDM Tech. Dig., pp. 607-610, 1992.
-
(1992)
IEDM Tech. Dig
, pp. 607-610
-
-
Oyama, K.1
Shirai, H.2
Kodama, N.3
Kanamori, K.4
Saitoh, K.5
Hisamune, Y.S.6
Okazawa, T.7
-
245
-
-
21644480739
-
8 Gb MLC (Multi-Level Cell) nand flash memory using 63 nm process technology
-
J.-H. Park, S.-H. Hur, J.-H. Leex, J.-T. Park; J.-S. Sel, J.-W. Kim, S.-B. Song, J.-Y. Lee, J.-H. Lee, S.-J Son, Y.-S. Kim, M.-C. Park, S.-J. Chai, J.-D. Choi, U.-I. Chung, J.-T. Moon, K.-T. Kim, K. Kim, B.-I. Ryu, "8 Gb MLC (Multi-Level Cell) NAND Flash Memory Using 63 nm Process Technology" in IEEE International Electron Devices Meeting, pp. 873-876, 2004.
-
(2004)
IEEE International Electron Devices Meeting
, pp. 873-876
-
-
Park, J.-H.1
Hur, S.-H.2
Leex, J.-H.3
Park, J.-T.4
Sel, J.-S.5
Kim, J.-W.6
Song, S.-B.7
Lee, J.-Y.8
Lee, J.-H.9
Son, S.-J.10
Kim, Y.-S.11
Park, M.-C.12
Chai, S.-J.13
Choi, J.-D.14
Chung, U.-I.15
Moon, J.-T.16
Kim, K.-T.17
Kim, K.18
Ryu, B.-I.19
-
246
-
-
0032097823
-
Degradation of thin tunnel gate oxide under constant fowler-nordheim current stress for a flash eeprom
-
June
-
Y. B. Park, D. K. Schroeder, "Degradation of Thin Tunnel Gate Oxide Under Constant Fowler-Nordheim Current Stress for a Flash EEPROM", IEEE Transaction on Electron Devices, Vol. 45, pp. 1361-1368, June 1998.
-
(1998)
IEEE Transaction on Electron Devices
, vol.45
, pp. 1361-1368
-
-
Park, Y.B.1
Schroeder, D.K.2
-
247
-
-
0031212918
-
Flash memory cells-an overview
-
August
-
P. Pavan, R. Bez, P. Olivo, E. Zanoni, "Flash Memory Cells-An Overview", Proc. IEEE, Vol. 85, pp. 1248-1271, August 1997.
-
(1997)
Proc. IEEE
, vol.85
, pp. 1248-1271
-
-
Pavan, P.1
Bez, R.2
Olivo, P.3
Zanoni, E.4
-
248
-
-
0029197224
-
Effects of erase source bias on flash eprom reliability
-
T. K. San, C. Kaya, T. P. Ma, "Effects of Erase Source Bias on Flash EPROM Reliability", IEEE Transaction on Electron Devices, Vol. 42, No. 1, pp. 150-159, 1995.
-
(1995)
IEEE Transaction on Electron Devices
, vol.42
, Issue.1
, pp. 150-159
-
-
San, T.K.1
Kaya, C.2
Ma, T.P.3
-
249
-
-
0035498583
-
Tail bit implications in advanced 2 transistors- flash memory device reliability
-
A. Scarpa, G. Tao, J. Dijkstra, F. G. Kuper, "Tail Bit Implications in Advanced 2 Transistors- Flash Memory Device Reliability", in Microelectronic Engineering, Vol. 59, No. 1-4, pp. 183-188, 2001.
-
(2001)
Microelectronic Engineering
, vol.59
, Issue.1-4
, pp. 183-188
-
-
Scarpa, A.1
Tao, G.2
Dijkstra, J.3
Kuper, F.G.4
-
250
-
-
0031146351
-
A compact on-chip ecc for low cost flash memories
-
May
-
T. Tanzawa, T. Tanaka, K. Takekuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takekuchi, K. Ohuchi, "A Compact On-Chip ECC for Low Cost Flash Memories", IEEE Journal of Solid-State Circuits, Vol. 32, pp. 662-669, May 1997.
-
(1997)
IEEE Journal of Solid-State Circuits
, vol.32
, pp. 662-669
-
-
Tanzawa, T.1
Tanaka, T.2
Takekuchi, K.3
Shirota, R.4
Aritome, S.5
Watanabe, H.6
Hemink, G.7
Shimizu, K.8
Sato, S.9
Takekuchi, Y.10
Ohuchi, K.11
-
251
-
-
0029224825
-
Improving program/erase endurance by controlling the inter-poly process in flash memory
-
M. Ushiyama, H. Miura, H. Yashima, T. Adachi, T. Nishimoto, K. Komori, Y. Kamigaki, M. Kato, H. Kume, Y. Ohji, "Improving Program/Erase Endurance by Controlling the Inter-poly Process in Flash Memory", in Proc. IRPS, pp. 18-23, 1995.
-
(1995)
Proc. IRPS
, pp. 18-23
-
-
Ushiyama, M.1
Miura, H.2
Yashima, H.3
Adachi, T.4
Nishimoto, T.5
Komori, K.6
Kamigaki, Y.7
Kato, M.8
Kume, H.9
Ohji, Y.10
-
252
-
-
0026137455
-
Two dimensionally inhomogeneous structure at gate electrode/gate insulator interface causing fowler-nordheim current deviation in nonvolatile memory
-
M. Ushiyama, Y. Ohji, T. Nishimoto, K. Komori, H. Murakoshi, H. Kume, S. Tachi, "Two Dimensionally Inhomogeneous Structure at Gate Electrode/Gate Insulator Interface Causing Fowler-Nordheim Current Deviation in Nonvolatile Memory", in Proc. IRPS, pp. 331-336, 1991.
-
(1991)
Proc. IRPS
, pp. 331-336
-
-
Ushiyama, M.1
Ohji, Y.2
Nishimoto, T.3
Komori, K.4
Murakoshi, H.5
Kume, H.6
Tachi, S.7
-
253
-
-
0025451991
-
A 35 ns 256 k CMOS EEPROM with error correcting circuitry
-
R. Vancu, L. Chen, R. L. Wan, T. Nguyen, C.-Y. Yang, W.-P.Lai, K.-F.Tang, A. Minhea, A. Renninger, G. Smarandoiu, "A 35 ns 256 k CMOS EEPROM with Error Correcting Circuitry", in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1990, pp. 64-65.
-
(1990)
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 64-65
-
-
Vancu, R.1
Chen, L.2
Wan, R.L.3
Nguyen, T.4
Yang, C.-Y.5
Lai, W.-P.6
Tang, K.-F.7
Minhea, A.8
Renninger, A.9
Smarandoiu, G.10
-
254
-
-
0023829362
-
Reliability performance of etox based flash memories
-
G. Verma, N. Mielke, "Reliability Performance of ETOX Based Flash Memories", in Proc. IRPS, pp. 158-166, 1988.
-
(1988)
Proc. IRPS
, pp. 158-166
-
-
Verma, G.1
Mielke, N.2
-
255
-
-
0027816862
-
Degradation mechanism of flash eeprom programming after program/erase cycles
-
S. Yamada, Y. Hiura, T. Yamane, K. Amemiya, Y. Ohshima, K. Yoshikawa, "Degradation Mechanism of Flash EEPROM programming after program/erase cycles", in IEDM Tech. Dig., pp. 23-26, 1993.
-
(1993)
IEDM Tech. Dig.
, pp. 23-26
-
-
Yamada, S.1
Hiura, Y.2
Yamane, T.3
Amemiya, K.4
Ohshima, Y.5
Yoshikawa, K.6
-
256
-
-
84954185679
-
A self-convergence erasing scheme for simple stacked gate flash EEPROM
-
S. Yamada, T. Suzuki, E. Obi, M. Oshikiri, K. Naruke, M. Wada, "A Self-Convergence Erasing Scheme for Simple Stacked Gate Flash EEPROM", in IEDM Tech. Dig., pp. 307-310, 1991.
-
(1991)
IEDM Tech. Dig
, pp. 307-310
-
-
Yamada, S.1
Suzuki, T.2
Obi, E.3
Oshikiri, M.4
Naruke, K.5
Wada, M.6
-
257
-
-
0029714969
-
Impact of cell threshold voltage distribution in the array of flash memories on scaled and multilevel flash cell design
-
K. Yoshikawa, "Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design", in Symposium on VLSI Technology Digest of Technical Papers, pp. 241-242, 1996.
-
(1996)
Symposium on VLSI Technology Digest of Technical Papers
, pp. 241-242
-
-
Yoshikawa, K.1
-
259
-
-
84892198271
-
-
US Patent US2002/0039418 A1, April
-
I. Dror, C. D. Gressel, M. Mostovoy, A. Molchanov, "Extending the Range of Computational Fields of Integers" in US Patent US2002/0039418 A1, April 2002.
-
(2002)
Extending the Range of Computational Fields of Integers
-
-
Dror, I.1
Gressel, C.D.2
Mostovoy, M.3
Molchanov, A.4
-
262
-
-
84892206737
-
-
US Patent US2004/0205095 A1, October
-
C. D. Gressel, A. Schevachman, E. Aizman, M. Slobodkin, S. Cooper, "Random Number Slip and Swap Generators" in US Patent US2004/0205095 A1, October 2004.
-
(2004)
Random Number Slip and Swap Generators
-
-
Gressel, C.D.1
Schevachman, A.2
Aizman, E.3
Slobodkin, M.4
Cooper, S.5
-
265
-
-
0030717379
-
Optimized arithmetic for reed-solomon encoders
-
June
-
C. Paar, "Optimized Arithmetic for Reed-Solomon Encoders" in ISIT, June 1997.
-
(1997)
ISIT
-
-
Paar, C.1
-
268
-
-
0036602029
-
The zeros of random polynomials: Further results and applications
-
June
-
R. Schober, W. H. Gerstacker, "The Zeros of Random Polynomials: Further Results and Applications" in IEEE Transactions on Communications, Vol. 50, June 2002.
-
(2002)
IEEE Transactions on Communications
, vol.50
-
-
Schober, R.1
Gerstacker, W.H.2
-
270
-
-
0026819224
-
Symbol error-correcting codes for computer memory systems
-
February
-
C. L. Chen, "Symbol Error-Correcting Codes for Computer Memory Systems" in IEEE Transactions on Computers, Vol. 46, February 1992.
-
(1992)
IEEE Transactions on Computers
, vol.46
-
-
Chen, C.L.1
-
271
-
-
0029723076
-
Symbol error correcting codes for memory applications
-
C. L. Chen, "Symbol Error Correcting Codes for Memory Applications" in IEEE Proceedings of FTCS, 1996.
-
(1996)
IEEE Proceedings of FTCS
-
-
Chen, C.L.1
-
272
-
-
0021392066
-
Error-correcting codes for semiconductor memory applications: A state-of-the-art-review
-
March
-
C. L. Chen, M. Y. Hsiao, "Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art-Review" in IBM Journal of Research and Development, March 1984.
-
(1984)
IBM Journal of Research and Development
-
-
Chen, C.L.1
Hsiao, M.Y.2
-
273
-
-
0026152418
-
An alternative to the hamming code in the class of sec-ded codes in semiconductor memory
-
May
-
A. A. Davydov, L. M. Tombak, "An Alternative to the Hamming Code in the Class of SEC-DED Codes in Semiconductor Memory" in IEEE Transactions on Information Theory, Vol. 37, May 1991.
-
(1991)
IEEE Transactions on Information Theory
, vol.37
-
-
Davydov, A.A.1
Tombak, L.M.2
-
274
-
-
84892328942
-
-
US Patent US2005/0160350 A1, July
-
I. Dror, M. Avraham, B. Dulgunov, E. Fumbarov, "Compact High-Speed Single-Bit Error- Correction Circuit" in US Patent US2005/0160350 A1, July 2005.
-
(2005)
Compact High-Speed Single-Bit Error- Correction Circuit
-
-
Dror, I.1
Avraham, M.2
Dulgunov, B.3
Fumbarov, E.4
-
276
-
-
4344701872
-
On-chip error correcting techniques for new-generation flash memories
-
April
-
S. Gregori, A. Cabrini, O. Khouri, G. Torelli, "On-Chip Error Correcting Techniques for New-Generation Flash Memories" in Proceedings of the IEEE, Vol. 91, April 2003.
-
(2003)
Proceedings of the IEEE
, vol.91
-
-
Gregori, S.1
Cabrini, A.2
Khouri, O.3
Torelli, G.4
-
277
-
-
0034876224
-
An error control code scheme for multilevel flash memories
-
San Jose, California (USA), August
-
S. Gregori, O. Khuori, R. Micheloni, G. Torelli, "An Error Control Code Scheme for Multilevel Flash Memories", 2001 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2001), San Jose, California (USA), August 2001, pp. 45-49.
-
(2001)
2001 IEEE International Workshop on Memory Technology, Design and Testing (MTDT 2001)
, pp. 45-49
-
-
Gregori, S.1
Khuori, O.2
Micheloni, R.3
Torelli, G.4
-
278
-
-
0031348803
-
A class of error control codes for byte organized memory systems - sbec-(sb+s)ed codes
-
January
-
M. Harmada, E. Fujiwara, "A Class of Error Control Codes for Byte Organized Memory Systems - SbEC-(Sb+S)ED Codes" in IEEE Transactions on Computers, Vol. 46, January 1997.
-
(1997)
IEEE Transactions on Computers
, vol.46
-
-
Harmada, M.1
Fujiwara, E.2
-
279
-
-
0032140032
-
A multipage cell architecture for high-speed programming multilevel nand flash memories
-
August
-
T. Ken, T. Tomoharu, T. Toru, "A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories" in IEEE Journal of Solid State Circuits, Vol. 33, August 1998.
-
(1998)
IEEE Journal of Solid State Circuits
, vol.33
-
-
Ken, T.1
Tomoharu, T.2
Toru, T.3
-
281
-
-
0027875436
-
Design of a fault-tolerant three-dimensional dynamic random-access memory with on-chip error-correcting circuit
-
December
-
P. Makumber, "Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit" in IEEE Transactions on Computers, Vol. 42, December 1993.
-
(1993)
IEEE Transactions on Computers
, vol.42
-
-
Makumber, P.1
-
282
-
-
0027875436
-
Design of a fault-tolerant three-dimensional dynamic random-access memory with on-chip error-correcting circuit
-
December
-
P. Mazumder, "Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit" in IEEE Transactions on Computers, Vol. 42, December 1993.
-
(1993)
IEEE Transactions on Computers
, vol.42
-
-
Mazumder, P.1
-
285
-
-
0029271693
-
Construction tecniques for systematic sed-ded codes with single byte error detection and partial correction capability for computer memory systems
-
March
-
L. Penzo, D. Sciuto, C. Silvano, "Construction Tecniques for Systematic SED-DED Codes with Single Byte Error Detection and Partial Correction Capability for Computer Memory Systems" in IEEE Transactions on Information Theory, Vol. 41, March 1995.
-
(1995)
IEEE Transactions on Information Theory
, vol.41
-
-
Penzo, L.1
Sciuto, D.2
Silvano, C.3
-
289
-
-
0031146351
-
A compact on-chip ecc for low cost flash memories
-
May
-
T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takeuchi, K. Ohuchi, "A Compact On-Chip ECC for Low Cost Flash Memories" in IEEE Journal of Solid-State Circuits, Vol. 32, May 1997.
-
(1997)
IEEE Journal of Solid-State Circuits
, vol.32
-
-
Tanzawa, T.1
Tanaka, T.2
Takeuchi, K.3
Shirota, R.4
Aritome, S.5
Watanabe, H.6
Hemink, G.7
Shimizu, K.8
Sato, S.9
Takeuchi, Y.10
Ohuchi, K.11
-
290
-
-
0031146351
-
A compact on-chip ecc for low cost flash memories
-
May
-
T. Toru, T. Ken, S. Riichiro, A. Seiichi, W. Hiroshi, H. Gertjan, S. Kazuhiro, S. Shinji, T. Yuji, O. Kazunori, "A Compact On-Chip ECC for low Cost Flash Memories" in IEEE Journal of Solid State Circuits, Vol. 32, May 1997.
-
(1997)
IEEE Journal of Solid State Circuits
, vol.32
-
-
Toru, T.1
Ken, T.2
Riichiro, S.3
Seiichi, A.4
Hiroshi, W.5
Gertjan, H.6
Kazuhiro, S.7
Shinji, S.8
Yuji, T.9
Kazunori, O.10
-
293
-
-
0032675339
-
New serial architecture for the berlekamp-massey algorithm
-
April
-
H.-C. Chang, C. B. Shung, "New Serial Architecture for the Berlekamp-Massey Algorithm" in IEEE Transactions on Communications, Vol. 47, April 1999.
-
(1999)
IEEE Transactions on Communications
, vol.47
-
-
Chang, H.-C.1
Shung, C.B.2
-
294
-
-
0035247672
-
A Reed-solomon product-code (RS-PC) decoder chip for DVD applications
-
February
-
H.-C. Chang, C. B. Shung, "A Reed-Solomon Product-Code (RS-PC) Decoder Chip for DVD Applications" in IEEE Journal of Solid-State Circuits, Vol. 36, February 2001.
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
-
-
Chang, H.-C.1
Shung, C.B.2
-
298
-
-
0024666843
-
A generalized euclidean algorithm for multisequence shift- register synthesis
-
May
-
G. L. Feng, K. K. Tzeng, "A Generalized Euclidean Algorithm for Multisequence shift- Register Synthesis" in IEEE Transactions on Information Theory, Vol. 35, May 1989.
-
(1989)
IEEE Transactions on Information Theory
, vol.35
-
-
Feng, G.L.1
Tzeng, K.K.2
-
299
-
-
0026219341
-
A generalization of the berlekamp-massey algorithm for multisequence shift-register synthesis with applications to decoding cyclic codes
-
September
-
G. L. Feng, K. K. Tzeng, "A Generalization of the Berlekamp-Massey Algorithm for Multisequence Shift-Register Synthesis with Applications to Decoding Cyclic Codes" in IEEE Transactions on Information Theory, Vol. 37, September 1991.
-
(1991)
IEEE Transactions on Information Theory
, vol.37
-
-
Feng, G.L.1
Tzeng, K.K.2
-
301
-
-
0030657199
-
Comparison of two algorithms for decoding bch codes
-
June
-
P. Fitzpatrick, S. M. Jennings, "Comparison of Two Algorithms for Decoding BCH Codes" in ISIT, June 1997.
-
(1997)
ISIT
-
-
Fitzpatrick, P.1
Jennings, S.M.2
-
303
-
-
0033183669
-
Improved decoding of reed-solomon and algebraic-geometry codes
-
September
-
V. Guruswami, M. Sudan, "Improved Decoding of Reed-Solomon and Algebraic-Geometry Codes" in IEEE Transactions on Information Theory, Vol. 46, September 1999.
-
(1999)
IEEE Transactions on Information Theory
, vol.46
-
-
Guruswami, V.1
Sudan, M.2
-
307
-
-
0035355188
-
Reed-solomon decoding algorithms for digital audio broadcasting in the am band
-
June
-
J. N. Laneman, C. E. W. Sundberg, "Reed-Solomon Decoding Algorithms for Digital Audio Broadcasting in the AM Band" in IEEE Transactions on Broadcasting, Vol. 47, June 2001.
-
(2001)
IEEE Transactions on Broadcasting
, vol.47
-
-
Laneman, J.N.1
Sundberg, C.E.W.2
-
309
-
-
84892238135
-
-
US Patent 5, 416, 786, May
-
Y. S. Lin, Y. S. Kang, "Error Correction Circuit for BCH Codewords" in US Patent 5, 416, 786, May 1995.
-
(1995)
Error Correction Circuit for BCH Codewords
-
-
Lin, Y.S.1
Kang, Y.S.2
-
310
-
-
84892286217
-
-
US Patent US20050050434
-
M. Lunelli, R. Micheloni, R. Ravasio, A. Marelli, "Method for Performing Error Corrections of Digital Information Codified as a Symbol Sequence", US Patent US20050050434, 2005.
-
(2005)
Method for Performing Error Corrections of Digital Information Codified as a Symbol Sequence
-
-
Lunelli, M.1
Micheloni, R.2
Ravasio, R.3
Marelli, A.4
-
311
-
-
84937740421
-
Shift-register synthesis and bch decoding
-
January
-
J. Massey, "Shift-Register Synthesis and BCH Decoding" in IEEE Transactions on Information Theory, Vol. 15, January 1969.
-
(1969)
IEEE Transactions on Information Theory
, vol.15
-
-
Massey, J.1
-
312
-
-
84891997917
-
-
US Patent US20060010363
-
R. Micheloni, R. Ravasio, A. Marelli, "Method and System for Correcting Low Latency Errors in Read and Write Non Volatile Memories, Particularly of the Flash Type", US Patent US20060010363, 2006.
-
(2006)
Method and System for Correcting Low Latency Errors in Read and Write Non Volatile Memories, Particularly of the Flash Type
-
-
Micheloni, R.1
Ravasio, R.2
Marelli, A.3
-
317
-
-
0032097867
-
Algorithm-based low-power and high-performance multimedia signal processing
-
June
-
K. J. Ray Liu, A. Y. Wu, A. Raghupathy, J. Chen, "Algorithm-Based Low-Power and High-Performance Multimedia Signal Processing" in Proceedings of the IEEE, Vol. 86, June 1998.
-
(1998)
Proceedings of the IEEE
, vol.86
-
-
Liu, K.J.R.1
Wu, A.Y.2
Raghupathy, A.3
Chen, J.4
-
318
-
-
0026222469
-
VLSI design of inverse-free berlekamp-massey algorithm
-
September
-
I. S. Reed, M. T. Shih, T. K. Truong, "VLSI Design of Inverse-Free Berlekamp-Massey Algorithm" in IEEE Proceedings, Vol. 138, September 1991.
-
(1991)
IEEE Proceedings
, vol.138
-
-
Reed, I.S.1
Shih, M.T.2
Truong, T.K.3
-
321
-
-
0034448927
-
Very high-speed reed-solomon decoders
-
June
-
D. V. Sarwate, N. R. Shanbhag, "Very High-Speed Reed-Solomon Decoders" in ISIT2000, June 2000.
-
(2000)
ISIT2000
-
-
Sarwate, D.V.1
Shanbhag, N.R.2
-
323
-
-
0015400365
-
A branching control circuit for berlekamp's bch decoding algorithm
-
September
-
D. D. Sullivan, "A Branching Control Circuit for Berlekamp's BCH Decoding Algorithm" in IEEE Transactions on Information Theory, September 1972.
-
(1972)
IEEE Transactions on Information Theory
-
-
Sullivan, D.D.1
-
325
-
-
0035334168
-
Fast algorithm for computing the roots of error locator polynomials up to degree 11 in reed-solomon decoders
-
May
-
T. K. Truong, J. H. Jeng, I. S. Reed, "Fast Algorithm for Computing the Roots of Error Locator Polynomials up to Degree 11 in Reed-Solomon Decoders" in IEEE Transactions on Communications, Vol. 49, May 2001.
-
(2001)
IEEE Transactions on Communications
, vol.49
-
-
Truong, T.K.1
Jeng, J.H.2
Reed, I.S.3
-
326
-
-
0024904182
-
Comparison of the motorola dsp56000 and the texas instruments tms320c25 digital signal processors for implementing a four error correcting (127, 99) bch error control code decoder
-
June
-
W. B. Weeks, W. D. Little, V. K. Bhargava, T. A. Gulliver, "Comparison of the Motorola DSP56000 and the Texas Instruments TMS320C25 Digital Signal Processors for Implementing a Four Error Correcting (127, 99) BCH Error Control Code Decoder" in IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, June 1989.
-
(1989)
IEEE Pacific Rim Conference on Communications, Computers and Signal Processing
-
-
Weeks, W.B.1
Little, W.D.2
Bhargava, V.K.3
Gulliver, T.A.4
-
327
-
-
0033100435
-
A new scalable vlsi architecture for reed-solomon decoders
-
March
-
W. Wilhelm, "A New Scalable VLSI Architecture for Reed-Solomon Decoders" in IEEE Journal of Solid-State Circuits, Vol. 34, March 1999.
-
(1999)
IEEE Journal of Solid-State Circuits
, vol.34
-
-
Wilhelm, W.1
-
328
-
-
0031646252
-
ECC performance of interleaved rs codes with burst errors
-
January
-
J. K. Wolf, "ECC Performance of Interleaved RS Codes with Burst Errors" in IEEE Transactions on Magnetics, Vol. 34, January 1998.
-
(1998)
IEEE Transactions on Magnetics
, vol.34
-
-
Wolf, J.K.1
-
329
-
-
84892242522
-
On the high-speed vlsi implementation of errors-and erasures correcting reed-solomon decoders
-
April
-
T. Zhang, K. K. Parthi, "On the High-Speed VLSI Implementation of Errors-and Erasures Correcting Reed-Solomon Decoders" in GVLVLSI, April 2002.
-
(2002)
GVLVLSI
-
-
Zhang, T.1
Parthi, K.K.2
-
334
-
-
0026390769
-
Closed solution of berlekamp's algorithm for fast decoding of bch codes
-
December
-
C. Kraft, "Closed Solution of Berlekamp's Algorithm for Fast Decoding of BCH Codes", IEEE Transactions on Communications, Vol. 39, December 1991.
-
(1991)
IEEE Transactions on Communications
, vol.39
-
-
Kraft, C.1
-
337
-
-
84892286217
-
-
US Patent US20050050434
-
M. Lunelli, R. Micheloni, R. Ravasio, A. Marelli, "Method for Performing Error Corrections of Digital Information Codified as a Symbol Sequence", US Patent US20050050434, 2005.
-
(2005)
Method for Performing Error Corrections of Digital Information Codified as a Symbol Sequence
-
-
Lunelli, M.1
Micheloni, R.2
Ravasio, R.3
Marelli, A.4
-
338
-
-
84891997917
-
-
US Patent US20060010363
-
R. Micheloni, R. Ravasio, A. Marelli, "Method and System for Correcting low Latency Errors in Read and Write Non Volatile Memories, Particularly of the Flash Type", US Patent US20060010363, 2006.
-
(2006)
Method and System for Correcting Low Latency Errors in Read and Write Non Volatile Memories, Particularly of the Flash Type
-
-
Micheloni, R.1
Ravasio, R.2
Marelli, A.3
-
341
-
-
39749172648
-
A 4Gb 2b/cell nand flash memory with embedded 5b bch ecc for 36mb/s system read throughput
-
San Francisco, February
-
R. Micheloni et al. "A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput", ISSCC Dig. Tech. Papers, San Francisco, February 2006.
-
(2006)
ISSCC Dig. Tech. Papers
-
-
Micheloni, R.1
-
346
-
-
0031146351
-
A compact on-chip ecc for low cost flash memories
-
May
-
T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takeuchi, K. Ohuchi, "A Compact On-Chip ECC for Low Cost Flash Memories", IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, May 1997.
-
(1997)
IEEE Journal of Solid-State Circuits
, vol.32
, Issue.5
-
-
Tanzawa, T.1
Tanaka, T.2
Takeuchi, K.3
Shirota, R.4
Aritome, S.5
Watanabe, H.6
Hemink, G.7
Shimizu, K.8
Sato, S.9
Takeuchi, Y.10
Ohuchi, K.11
-
348
-
-
0020748740
-
The construction of fast, high-rate, soft decision block decoders
-
May
-
E. R. Berlekamp, "The Construction of Fast, High-Rate, Soft Decision Block Decoders" in IEEE Transactions on Information Theory, Vol. 29, May 1983.
-
(1983)
IEEE Transactions on Information Theory
, vol.29
-
-
Berlekamp, E.R.1
-
350
-
-
0028320019
-
New time domain errors and erasures decoding algorithm for bch codes
-
January
-
P. Fitzpatrick, "New Time Domain Errors and Erasures Decoding Algorithm for BCH Codes" in Electronics Letters, Vol. 30, January 1994.
-
(1994)
Electronics Letters
, vol.30
-
-
Fitzpatrick, P.1
-
352
-
-
84892225306
-
-
US 2007/0234164, October
-
V. Intini, A. Marelli, R. Ravasio, R. Micheloni, "Reading Method of a Memory Device with Embedded Error-Correcting Code and Memory Device With Embedded Error- Correcting Code" in US 2007/0234164, October 2007.
-
(2007)
Reading Method of a Memory Device with Embedded Error-Correcting Code and Memory Device with Embedded Error- Correcting Code
-
-
Intini, V.1
Marelli, A.2
Ravasio, R.3
Micheloni, R.4
-
353
-
-
0031234379
-
On acceptance criterion for efficient successive errors-and-erasures decoding of reed-solomon and bch codes
-
September
-
N. Kamiya, "On Acceptance Criterion for Efficient Successive Errors-and-Erasures Decoding of Reed-Solomon and BCH Codes" in IEEE Transactions on Information Theory, Vol. 43, September 1993.
-
(1993)
IEEE Transactions on Information Theory
, vol.43
-
-
Kamiya, N.1
-
354
-
-
0035094214
-
On algebraic soft-decision decoding algorithms for bch codes
-
January
-
N. Kamiya, "On Algebraic Soft-Decision Decoding Algorithms for BCH Codes" in IEEE Transactions on Information Theory, Vol. 47, January 2001.
-
(2001)
IEEE Transactions on Information Theory
, vol.47
-
-
Kamiya, N.1
-
355
-
-
0031275491
-
A class of array codes correcting multiple column erasures
-
November
-
O. Keren, S. Litsyn, "A Class of Array Codes Correcting Multiple Column Erasures" in IEEE Transactions on Information Theory, Vol. 43, November 1997.
-
(1997)
IEEE Transactions on Information Theory
, vol.43
-
-
Keren, O.1
Litsyn, S.2
-
356
-
-
0030148636
-
Undected error probabilites of binary primitive bch codes for both error correction and detection
-
May
-
M. G. Kim, J. H. Lee, "Undected Error Probabilites of Binary Primitive BCH Codes for Both Error Correction and Detection" in IEEE Transactions on Communications, Vol. 44, May 1996.
-
(1996)
IEEE Transactions on Communications
, vol.44
-
-
Kim, M.G.1
Lee, J.H.2
-
358
-
-
37549006492
-
The impact of random telegraph signals on the scaling of multilevel flash memories
-
H. Kurata, K. Otsuga, A. Kotabe, S. Kajiyama, T. Osabe, Y. Sasago, S. Narumi, K. Tokami, S. Kamohara, O. Tsuchiya, "The Impact of Random Telegraph signals on the Scaling of Multilevel Flash Memories" in IEEE Symposium on VLSI Circuits Digest of Technical Papers, 2006.
-
(2006)
IEEE Symposium on VLSI Circuits Digest of Technical Papers
-
-
Kurata, H.1
Otsuga, K.2
Kotabe, A.3
Kajiyama, S.4
Osabe, T.5
Sasago, Y.6
Narumi, S.7
Tokami, K.8
Kamohara, S.9
Tsuchiya, O.10
-
359
-
-
0020827239
-
Simplified correlation decoding by selecting possible codewords using erasure information
-
September
-
H. Tanaka, K. Kakigahara, "Simplified Correlation Decoding by Selecting Possible Codewords Using Erasure Information" in IEEE Transactions on Information Theory, Vol. 29, September 1983.
-
(1983)
IEEE Transactions on Information Theory
, vol.29
-
-
Tanaka, H.1
Kakigahara, K.2
-
360
-
-
0020827239
-
Simplified correlation decoding by selecting possible codewords using erasure information
-
September
-
H. Tanaka, K. Kakigahara, "Simplified Correlation Decoding by Selecting Possible Codewords Using Erasure Information" in IEEE Transactions on Information Theory, Vol. 29, September 1983.
-
(1983)
IEEE Transactions on Information Theory
, vol.29
-
-
Tanaka, H.1
Kakigahara, K.2
-
361
-
-
0032633789
-
Extended hamming and bch soft decision decoders for mobile data applications
-
March 1999
-
T. L. Tapp, A. A. Luna, X. Wang, S. B. Wicker, "Extended Hamming and BCH Soft Decision Decoders for Mobile Data Applications" in IEEE Transactions on Communications, Vol. 47, March 1999.
-
IEEE Transactions on Communications
, vol.47
-
-
Tapp, T.L.1
Luna, A.A.2
Wang, X.3
Wicker, S.B.4
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