Small area parallel chien search architectures for long BCH codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 5, 2004, Pages 545-549

  Chen, Yanni ^a,b   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

BCH (Bose Chaudhuri Hochquenghem) code; Chien search; Low complexity

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DECODING; ERROR CORRECTION; ITERATIVE METHODS; LOGIC DESIGN;

BCH (BOSE-CHAUDHURI-HOCHQUENGHEM) CODES; CHIEN SEARCH; DECODERS; LOW-COMPLEXITY;

MULTIPLYING CIRCUITS;

EID: 2542485570     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.826203     Document Type: Article

References (6)

1. "Forward Error Correction for Submarine Systems," Telecommunication Standardization Section, International Telecommunication Union, Geneva, Switzerland, ITU-T Recommendation G.975, Oct. 2000.
2. L. Song, M.-L. Yu, and M. S. Shaffer, "10- and 40-Gb/s forward error correction devices for optical communications," IEEE J. Solid-State Circuits, vol. 37, pp. 1565-1573, Nov. 2002.
3. S. B. Wicker, Error Control Systems for Digital Communication and Storage. Englewood Cliffs, NJ: Prentice-Hall, 1995.
4. H. C. Chang, C. C. Lin, and C. Y. Lee, "A low power Reed-Solomon decoder for STM-16 optical communications," in IEEE Proc. Asia-Pacific Conf. ASIC, 2002, pp. 351-354.
5. C. Paar, "Optimized arithmetic for Reed-Solomon encoders," in Proc. IEEE Int. Sym. Information Theory, 1997, p. 250.
6. M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, "Multiple constant multiplications: Efficient and versatile framework and algorithms for exploring common subexpression elimination," IEEE Trans. Computer-Aided Design, vol. 15, pp. 151-165, Feb. 1996.