8Gb MLC (multi-level cell) NAND flash memory using 63nm process technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 873-876

  Park, Jong Ho ^a   Hur, Sung Hoi ^a   Lee, Joon Hee ^a   Park, Jin Taek ^a   Sel, Jong Sun ^a   Kim, Jong Won ^a   Song, Sang Bin ^a   Lee, Jung Young ^a   Lee, Ji Hwon ^a   Son, Suk Joon ^a   Kim, Yong Seok ^a   Park, Min Cheol ^a   Chai, Soo Jin ^a   Choi, Jung Dal ^a   Chung, U In ^a   Moon, Joo Tae ^a   Kim, Kyeong Tae ^a   Kim, Kinam ^a   Ryu, Byung Il ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC FIELDS; ELECTRIC RESISTANCE; ETCHING; FLASH MEMORY; LITHOGRAPHY; MASKS; OPTIMIZATION; PHASE SHIFT; POLYSILICON; THRESHOLD VOLTAGE; TRANSMISSION ELECTRON MICROSCOPY; FLUORINE COMPOUNDS; MEMORY ARCHITECTURE; NAND CIRCUITS;

63NM PROCESS TECHNOLOGY; OFF-AXIS ILLUMINATION (OAI); OPTICAL PROXIMITY CORRECTION (OPC); PHASE SHIFT MASKS (PSM);

LOGIC GATES; TUNGSTEN;

63NM PROCESS TECHNOLOGY; ARF LITHOGRAPHY; CRITICAL LAYER; DESIGN RULES; MASS STORAGE; MULTILEVELS; NAND FLASH MEMORY; OFF-AXIS ILLUMINATION; SELF-ALIGNED; UNIT CELL SIZE;

EID: 21644480739     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. D. Choi, et al., "Highly manufacturable 1Gb NAND flash using 0.12μm process technology," IEDM Tech. Dig., pp. 25-28, 2001.
2. S. Keeny et al., "A 130 nm generation high density Etox flash memory technology," IEDM Tech. Dig., pp. 41-44, 2001.
3. Y.S. Yim et al., "70nm NAND flash technology with 0.025 μm2 cell size for 4Gb flash memory," IEDM Tech. Dig., pp. 819-822, 2003.
4. J. D. Lee, et. al., "Effects of floating-gate interference on NAND flash memory cell operation," IEEE EDL., Vol. 23, No. 5, pp. 264-266, 2002.