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Volumn 48, Issue , 2005, Pages 46-47

An 8Gb multi-level NAND flash memory with 63nm STI CMOS process technology

Author keywords

[No Author keywords available]

Indexed keywords


EID: 28144453513     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (27)

References (5)
  • 1
    • 0035506993 scopus 로고    scopus 로고
    • A dual-mode NAND flash memory: 1Gb multilevel and high-performance 512Mb single-level modes
    • Nov.
    • T. H. Cho et al., "A Dual-Mode NAND Flash Memory: 1Gb Multilevel and High-Performance 512Mb Single-Level Modes," IEEE J. Solid-State Circuits vol. 36, no. 11, pp. 1700-1706, Nov., 2001.
    • (2001) IEEE J. Solid-state Circuits , vol.36 , Issue.11 , pp. 1700-1706
    • Cho, T.H.1
  • 2
    • 2442700147 scopus 로고    scopus 로고
    • A 3.3V, 4Gb, four-level NAND flash memory with 0.09μm CMOS technology
    • Feb.
    • S.J. Lee at al, "A 3.3V, 4Gb, Four-Level NAND Flash Memory with 0.09μm CMOS technology," ISSCC Dig. Tech. Papers, pp. 52-53, Feb., 2004.
    • (2004) ISSCC Dig. Tech. Papers , pp. 52-53
    • Lee, S.J.1
  • 3
    • 0038306352 scopus 로고    scopus 로고
    • A 1.8V, 2Gb NAND flash memory for mass storage applications
    • Feb.
    • J. Lee at al, "A 1.8V, 2Gb NAND Flash Memory for Mass Storage Applications," ISSCC Dig. Tech. Papers, vol 46, pp. 290-291, Feb., 2003.
    • (2003) ISSCC Dig. Tech. Papers , vol.46 , pp. 290-291
    • Lee, J.1
  • 4
    • 0028538112 scopus 로고
    • A quick intelligent page-programming architecture and a shielded bitline sensing method for 3V-only NANA flash memory
    • Nov.
    • T. Tanaka et al., "A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3V-only NANA Flash Memory," IEEE J. of Solid-State Circuits, vol. 29, no. 11, pp. 1149-1156, Nov., 1994.
    • (1994) IEEE J. of Solid-state Circuits , vol.29 , Issue.11 , pp. 1149-1156
    • Tanaka, T.1
  • 5
    • 0029251968 scopus 로고
    • A 3.3V 32Mb NAND flash memory with incremental step pulse programming scheme
    • Feb.
    • K.D. Suh et al., "A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," in ISSCC Dig. Tech. Papers, pp. 128-129, Feb., 1995.
    • (1995) ISSCC Dig. Tech. Papers , pp. 128-129
    • Suh, K.D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.