An 8Gb multi-level NAND flash memory with 63nm STI CMOS process technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages 46-47

  Byeon, Dae Seok ^a   Lee, Sung Soo ^a   Lim, Young Ho ^a   Park, Jin Sung ^a   Han, Wook Kee ^a   Kwak, Pan Suk ^a   Kim, Dong Hwan ^a   Chae, Dong Hyuk ^a   Moon, Seung Hyun ^a   Lee, Seung Jae ^a   Cho, Hyun Chul ^a   Lee, Jung Woo ^a   Kim, Moo Sung ^a   Yang, Joon Sung ^a   Park, Young Woo ^a   Bae, Duk Won ^a   Choi, Jung Dal ^a   Hur, Sung Hoi ^a   Suh, Kang Deog ^a  

^a Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144453513     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. T. H. Cho et al., "A Dual-Mode NAND Flash Memory: 1Gb Multilevel and High-Performance 512Mb Single-Level Modes," IEEE J. Solid-State Circuits vol. 36, no. 11, pp. 1700-1706, Nov., 2001.
2. S.J. Lee at al, "A 3.3V, 4Gb, Four-Level NAND Flash Memory with 0.09μm CMOS technology," ISSCC Dig. Tech. Papers, pp. 52-53, Feb., 2004.
3. J. Lee at al, "A 1.8V, 2Gb NAND Flash Memory for Mass Storage Applications," ISSCC Dig. Tech. Papers, vol 46, pp. 290-291, Feb., 2003.
4. T. Tanaka et al., "A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3V-only NANA Flash Memory," IEEE J. of Solid-State Circuits, vol. 29, no. 11, pp. 1149-1156, Nov., 1994.
5. K.D. Suh et al., "A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," in ISSCC Dig. Tech. Papers, pp. 128-129, Feb., 1995.