High-speed architectures for Reed-Solomon decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 5, 2001, Pages 641-655

  Sarwate, Dilip V ^a,b   Shanbhag, Naresh R ^a,b  

^a IEEE   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Berlekamp Massey algorithm; Interleaved codes; Pipelined decoders; Reed Solomon codes; Systolic architectures

Indexed keywords

REED-SOLOMON DECODERS;

ADDERS; ALGORITHMS; ITERATIVE METHODS; POLYNOMIALS; PROGRAM PROCESSORS; VLSI CIRCUITS;

DECODING;

EID: 0035473059     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.953498     Document Type: Article

References (19)

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