Area-efficient layout design for CMOS output transistors

IEEE Transactions on Electron Devices

Volumn 44, Issue 4, 1997, Pages 635-645

  Ker, Ming Dou ^a,c   Wu, Chung Yu ^b,c   Wu, Tain Shun ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^c IEEE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC CURRENTS; ELECTRIC DISCHARGES; INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; OXIDES;

DRAIN TO BULK PARASITIC CAPACITANCE; LIGHTLY DOPED DRAIN STRUCTURE; OCTAGON TYPE LAYOUT;

CMOS INTEGRATED CIRCUITS;

EID: 0031121346     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.563369     Document Type: Article

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