Channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1648-1654

  Atsumi, Shigeru ^a,b   Umezawa, Akira ^a,b   Tanzawa, Tooru ^a   Taura, Tadayuki ^a   Shiga, Hitoshi ^a   Takano, Yoshinori ^a,c   Miyaba, Takeshi ^a,d   Matsui, Michiharu ^a   Watanabe, Hiroshi ^a,b   Isobe, Kazuaki ^a   Kitamura, Shota ^a   Yamada, Seiji ^a   Saito, Masanobu ^a   Mori, Seiichi ^a   Watanabe, Toshiharu ^a  

^a TOSHIBA CORPORATION   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c WASEDA UNIVERSITY   (Japan)

^d IBARAKI UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; DECODING; FLASH MEMORY; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS;

BITLINE DIRECT SENSING SCHEME; BLOCK DECODER CIRCUIT; CHANNEL ERASING SCHEME; NOR FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY; SENSE AMPLIFIER CIRCUIT; SHMOO PLOT; WORDLINE BOOSTED VOLTAGE POOLING METHOD;

PROM;

EID: 0034314527     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881211     Document Type: Article

References (16)

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