Survey on flash technology with specific attention to the critical process parameters related to manufacturing

Proceedings of the IEEE

Volumn 91, Issue 4, 2003, Pages 503-521

  Ginami, Giancarlo ^a,b   Canali, Danilo ^a,c,d   Fattori, Davide ^a   Girardi, Giuliana ^a   Scintu, Petronilla ^a   Tarchini, Laura ^a   Tricarico, Domenica ^a  

^a STMICROELECTRONICS   (Italy)

^b Central R and D Department

^c Device Engineering Group

^d EWS Testing for High Density Flash Memory ^*

Author keywords

CMOS transistor; CMOS transistor scaling; Flash memory; Flash technology; Memory cell; Memory cell scaling; Non volatile memory

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; LITHOGRAPHY; LOGIC DESIGN; TRANSISTORS;

CHEMICAL MECHANICAL PLANARIZATION; CMOS TRANSISTOR SCALING; FLASH TECHNOLOGY; MEMORY CELL; MEMORY CELL SCALING; NON-VOLATILE MEMORY;

FLASH MEMORY;

EID: 33646843945     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2003.811703     Document Type: Review

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