A 1.8V 128Mb 125MHz multi-level cell flash memory with flexible read while write

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Elmhurst, D ^a   Bains, R ^a   Bressie, T ^a   Bueb, C ^a   Carrieri, C ^a   Chauhan, B ^a   Chrisman, N ^a   Dayley, M ^a   De Luna, R ^a   Fan, K ^a   Goldman, M ^a   Govindu, P ^a   Huq, A ^a   Khandaker, M ^a   Kreifels, J ^a   Krishnamachari, S ^a   Lavapie, P ^a   Loe, K ^a   Ly, T ^a   Marvin, F ^a   Melcher, R ^a   Monasa, S ^a   Nguyen, Q ^a   Pathak, B ^a   Proescholdt, A ^a   Rahman, T ^a   Srinivasan, B ^a   Sundaram, R ^a   Walimbe, P ^a   Ward, D ^a   Dave, ^a   Zeng, R ^a   Zhang, H ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CAPACITANCE; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; LITHOGRAPHY; SIGNAL PROCESSING; TRANSISTORS;

CONTINUOUS BURST OPERATION; MULTILEVEL CELL STORAGE; NON-VOLATILE STORAGE; READ WHILE WRITE ARCHITECTURE;

FLASH MEMORY;

EID: 0037630791     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Bauer, M et al., "A Multilevel-Cell 32Mb Flash Memory," ISSCC Digest of Technical Papers, pp. 132-133, 1995.
2. Pathak, B. et al., "A 1.8V 100MHz Flexible Read While Write Flash Memory," ISSCC Digest of Technical Papers, pp. 32-33, 2001.
3. Castro, H. A. et al., "A 125MHz Burst Mode 0.18μm 128Mbit 2Bits per Cell Flash Memory," VLSI Symposium, July 2002.