A New Scalable VLSI Architecture for Reed-Solomon Decoders

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 3, 1999, Pages 388-396

  Wilhelm, Wolfgang ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

Reed Solomon decoder; Time sharing strategies

Indexed keywords

DECODING; DIGITAL CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

REED-SOLOMON DECODERS;

VLSI CIRCUITS;

EID: 0033100435     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.748191     Document Type: Article

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