A multipage cell architecture for high-speed programming multilevel NAND flash memories

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 8, 1998, Pages 1228-1237

  Takeuchi, Ken ^a,b   Tanaka, Tomoharu ^a,c   Tanzawa, Toni ^a  

^a TOSHIBA CORPORATION   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c UNIVERSITY OF TSUKUBA   (Japan)

Author keywords

Flash memory; High speed programming; Multi level cell; NAND flash memory

Indexed keywords

COMPUTER PROGRAMMING; COMPUTER SOFTWARE; DIGITAL INTEGRATED CIRCUITS; NAND CIRCUITS; PERFORMANCE;

FLASH MEMORY;

DATA STORAGE EQUIPMENT;

EID: 0032140032     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.705361     Document Type: Article

References (13)

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