3.3V 128Mb multi-level NAND flash memory for mass storage applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 32-33

  Jung, Tae Sung ^a   Choi, Young Joon ^a   Suh, Kang Deog ^a   Suh, Byung Hoon ^a   Kim, Jin Ki ^a   Lim, Young Ho ^a   Koh, Yong Nam ^a   Park, Jong Wook ^a   Lee, Ki Jong ^a   Park, Jung Hoon ^a   Park, Kee Tae ^a   Kim, Jang Rae ^a   Lee, Jeong Hyong ^a   Lim, Hyung Kyu ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BACKGROUND PATTERN DEPENDENCY; FLASH MEMORY; INCREMENTAL STEP PULSE PROGRAMMING; MASS STORAGE; SENSE AND LATCH UNIT; VIRTUAL GROUND LINE;

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC WAVEFORMS; NAND CIRCUITS; OPTIMIZATION; SCHEMATIC DIAGRAMS; SPURIOUS SIGNAL NOISE; TRANSISTORS;

DIGITAL STORAGE;

EID: 0030081176     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)