3.4-Mbyte/sec programming 3-level NAND flash memory saving 40% die size per bit

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1997, Pages 65-66

  Tanaka, Tomoharu ^a   Tanzawa, Toru ^a   Takeuchi, Ken ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR CORRECTION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; NAND CIRCUITS; PULSE GENERATORS;

FLASH MEMORIES; PROGRAM PULSES;

NONVOLATILE STORAGE;

EID: 0031344954     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)