On the high-speed VLSI implementation of errors-and-erasures correcting Reed-Solomon decoders

GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2002, Pages 89-93

  Zhang, Tong ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Berlekamp massey algorithm; Erasure; Reed solomon codes; VLSI architectures

Indexed keywords

ERRORS; HARDWARE; INTEGRATED CIRCUIT TESTING; REED-SOLOMON CODES; VLSI CIRCUITS;

BERLEKAMP-MASSEY ALGORITHM; ERASURE; ERRORS AND ERASURES CORRECTING; HARDWARE ARCHITECTURE; OPERATION SCHEDULING; REED SOLOMON DECODER; REED-SOLOMON DECODING; VLSI ARCHITECTURES;

DECODING;

EID: 84892242522     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505306.505326     Document Type: Conference Paper

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