40-mm2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 11, 2000, Pages 1655-1667

  Campardo, Giovanni ^a,c   Micheloni, Rino ^a   Commodaro, Stefano ^a   Yero, Emilio ^a   Zammattio, Matteo ^a   Mognoni, Sabina ^a   Sacco, Andrea ^a   Picca, Massimiliano ^a   Manstretta, Alessandro ^a   Scotti, Marco ^a   Motta, Ilaria ^a   Golla, C ^a   Pierin, Andrea ^a   Bez, Roberto ^a   Grossi, Alessandro ^a   Modelli, Alberto ^a   Visconti, Angelo ^a   Khouri, Osama ^a,b   Torelli, Guido ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

^c UNIVERSITY OF MILAN   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ERROR CORRECTION; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; THRESHOLD VOLTAGE;

CHANNEL HOT ELECTRON; NOR FLASH MEMORY; SHALLOW TRENCH ISOLATION; SHMOO PLOT; STAIRCASE GATE VOLTAGE PROGRAMMING;

FLASH MEMORY;

EID: 0034316131     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.881212     Document Type: Article

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