A class of error control codes for byte organized memory systems - SbEC-(Sb+S)ED Codes

IEEE Transactions on Computers

Volumn 46, Issue 1, 1997, Pages 105-109

  Hamada, Mitsuru ^a   Fujiwara, Eiji ^b,c  

^a UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^c IEEE   (Japan)

Author keywords

Byte; Error correcting code; Minimum polynomial; Soft error; Subfield

Indexed keywords

CODES (SYMBOLS); ERROR CORRECTION; ERROR DETECTION; POLYNOMIALS;

BYTE ORGANIZED MEMORY SYSTEMS; ERROR CONTROL CODES; SOFT ERRORS;

SEMICONDUCTOR STORAGE;

EID: 0031348803     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.559809     Document Type: Article

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