A triple-well architecture for low-voltage operation in submicron cmos devices

European Solid-State Device Research Conference

Volumn , Issue , 1996, Pages 613-616

  Auricchio, C ^a   Bez, R ^a   Losavio, A ^a   Maurelli, A ^a   Sala, C ^a   Zabberoni, P ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

LOW VOLTAGE OPERATION; SUBMICRON CMOS; TRIPLE WELL;

EID: 0004427465     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. J. O. Borland and R. Koelsh, Solid State Technology, pag.1, December 1993.
2. N. Ajikaet al., IEDM Tech. Dig., 5.7.1, pag. 115, 1990.
3. T. Jinbo et al., IEEE Journal of Solid State Circuits, 27, pag. 1547, 1992.
4. S. Kobayashi et al., VLSI Circuit Symposium, 12.1, pag.97, 1993.
5. A. Umezawa, IEEE Journal of Solid State Circuits, 27, pag. 1540, 1992.