On-chip error correcting techniques for new-generation flash memories

Proceedings of the IEEE

Volumn 91, Issue 4, 2003, Pages 602-616

  Gregori, Stefano ^a,b   Cabrini, Alessandro ^c   Khouri, Osama ^d   Torelli, Guido ^a,c,e  

^a IEEE   (United States)

^b The University of Texas at Dallas   (United States)

^c UNIVERSITY OF PAVIA   (Italy)

^d STMICROELECTRONICS   (Italy)

^e Italian Association of Electrical and Electronics Engineers (AEI)   (Italy)

Author keywords

Error control codes; Flash memories; Multilevel storage; Polyvalent codes; Reliability improvement

Indexed keywords

DATA PROCESSING; DATA STORAGE EQUIPMENT; DECODING; ENCODING (SYMBOLS); ERROR CORRECTION; MOS DEVICES;

ERROR CONTROL CODES; MULTILEVEL (ML) FLASH MEMORIES; MULTILEVEL STORAGE; POLYVALENT CODES; RELIABILITY IMPROVEMENT;

FLASH MEMORY;

EID: 4344701872     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2003.811709     Document Type: Review

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