Low power/high speed design of a Reed Solomon decoder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1997, Pages 2060-2063

  Raghupathy, Arun ^a   Liu, K J Ray ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CODING ERRORS; COMPUTATIONAL METHODS; DECODING; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS;

BERLEKAMP MASSEY DECODING ALGORITHMS; REED SOLOMON DECODERS;

VLSI CIRCUITS;

EID: 0030705679     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)