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Volumn 35, Issue 5, 2000, Pages 672-680

A source-line programming scheme for low-voltage operation NAND flash memories

Author keywords

Flash memory; Low voltage operation; Nand flash memory; Source line programming

Indexed keywords


EID: 0034179167     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.841463     Document Type: Article
Times cited : (20)

References (12)
  • 2
    • 0023563047 scopus 로고
    • New ultra high density EPROM and flash EEPROM with NAND structured cell, in
    • F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, New ultra high density EPROM and flash EEPROM with NAND structured cell, in IEEE Tech. Dig. IEDM1987, pp. 552-555.
    • (1987) IEEE Tech. Dig. IEDM , pp. 552-555
    • Masuoka, F.1    Momodomi, M.2    Iwata, Y.3    Shirota, R.4
  • 7
    • 84886448036 scopus 로고    scopus 로고
    • A novel isolation-scaling technology for NAND EEPROM's with the minimized program disturbance, in
    • S. Satoh, H. Hagiwara, T. Tanzawa, K. Takeuchi, and R. Shirota, A novel isolation-scaling technology for NAND EEPROM's with the minimized program disturbance, in IEEE Tech. Dig. 1EDM1997, pp. 291-294.
    • (1997) IEEE Tech. Dig. 1EDM , pp. 291-294
    • Satoh, S.1    Hagiwara, H.2    Tanzawa, T.3    Takeuchi, K.4    Shirota, R.5
  • 8
    • 0032625431 scopus 로고    scopus 로고
    • A negative Fth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories
    • May
    • K. Takeuchi, S. Satoh, T. Tanaka, K. Imamiya, and K. Sakui, A negative Fth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories, IEEE J. Solid-State Circuits, vol. 34, pp. 675-684, May 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , pp. 675-684
    • Takeuchi, K.1    Satoh, S.2    Tanaka, T.3    Imamiya, K.4    Sakui, K.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.