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Volumn 32, Issue 6, 1997, Pages 852-860

Efficiency improvement in charge pump circuits

Author keywords

Charge pump; CMOS analog integrated circuit; Latch up

Indexed keywords

ELECTRIC BREAKDOWN; ELECTRIC SWITCHES; ENERGY DISSIPATION; FREQUENCY CONVERTER CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; LINEAR INTEGRATED CIRCUITS;

EID: 0031166547     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.585287     Document Type: Article
Times cited : (132)

References (7)
  • 1
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    • June
    • J. F. Dickson "On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique." IEEE J. Solid-State Circuits, vol. SC-11, pp. 374-378, June 1976.
    • (1976) IEEE J. Solid-State Circuits , vol.SC-11 , pp. 374-378
    • Dickson, J.F.1
  • 2
    • 0019076599 scopus 로고
    • An on-chip back-bias generator for MOS dynamic memory
    • Oct.
    • W. L. Martino, Jr. et al., "An on-chip back-bias generator for MOS dynamic memory," IEEE J. Solid-State Circuits, vol. SC-15, pp. 820-825, Oct. 1980.
    • (1980) IEEE J. Solid-State Circuits , vol.SC-15 , pp. 820-825
    • Martino Jr., W.L.1
  • 3
    • 0030081947 scopus 로고    scopus 로고
    • 1.2V CMOS switch-capacitor circuits
    • Feb.
    • J. T. Wu et al. "1.2V CMOS switch-capacitor circuits," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 388-389.
    • (1996) ISSCC Dig. Tech. Papers , pp. 388-389
    • Wu, J.T.1
  • 4
    • 0028560793 scopus 로고
    • Charge pump for optimal, dynamic range filter
    • Apr.
    • G. L. E. Monna et al., "Charge pump for optimal, dynamic range filter," in Proc. ISCAS95, Apr. 1995, pp. 747-750.
    • (1995) Proc. ISCAS95 , pp. 747-750
    • Monna, G.L.E.1
  • 5
    • 84865942144 scopus 로고    scopus 로고
    • "Integrated dual charge pump power supply and rs-232 transmitter/receiver," U.S. Patent 4897774, Jan. 1990
    • D. Bingham et al., "Integrated dual charge pump power supply and rs-232 transmitter/receiver," U.S. Patent 4897774, Jan. 1990.
    • Bingham, D.1
  • 7
    • 0026204463 scopus 로고
    • High speed, high reliability circuit design for megabit DRAM
    • Aug.
    • P. Gillingham et al., "High speed, high reliability circuit design for megabit DRAM," IEEE J. Solid-State Circuits, vol. 26, no. 8, pp. 1171-1175, Aug. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.8 , pp. 1171-1175
    • Gillingham, P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.