Erratic erase in flash memories - Part II: Dependence on operating conditions

IEEE Transactions on Electron Devices

Volumn 50, Issue 4, 2003, Pages 1015-1021

  Chimenton, Andrea ^a   Olivo, Piero ^a  

^a UNIVERSITY OF FERRARA   (Italy)

Author keywords

Erasing operation; Flash memories; Integrated circuit reliability; Semiconductor memories

Indexed keywords

ELECTRIC CHARGE; GATES (TRANSISTOR); INTEGRATED CIRCUITS; INTERFACES (MATERIALS); NUMERICAL METHODS; THERMAL STRESS; THRESHOLD VOLTAGE;

SEMICONDUCTOR MEMORIES;

FLASH MEMORY;

EID: 0037480823     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.812099     Document Type: Article

References (11)

1. T. C. Ong, A. Fazio, N. Mielke, S. Pan, N. Righos, G. Atwood, and S. Lai, "Erratic erase in ETOX™ flash memory array," in VLSI Symp. Tech., 1993, pp. 83-84.
2. C. Dunn, C. Kaya, T. Lewis, T. Strauss, J. Schreck, P. Hefley, M. Middendorf, and T. San, "Flash EPROM disturb mechanisms," in Proc. Int. Rel. Phys. Symp., 1994, pp. 299-299.
3. K. Kobayashi, A. Teramoto, M. Hirayama, and Y. Fujita, "Model for the substrate hole current based on thermoionic hole emission from the anode during Fowler-Nordheim electron tunneling in n-channel metal-oxide-semiconductor field-effect transistors," J. Appl. Phys., vol. 77, pp. 3277-3282, Apr. 1994.
4. A. Chimenton and P. Olivo, "Erratic erase in Flash memories - Part I: Basic experimental and statistical characterization," IEEE Trans. Electron Devices, vol. 50, pp. 1009-1014, Apr. 2003, to be published.
5. P. Pellati and P. Olivo, "Automated test equipment for research on nonvolatile memories," IEEE Trans. Instrum. Meas., vol. 50, pp. 1162-1166, Oct. 2001.
6. K. Yoshikawa et al., "Comparison of current flash EEPROM erasing methods: Stability and how to control," in IEDM Tech. Dig., 1992, p. 595.
7. R. Bez, D. Cantarelli, L. Moioli, G. Ortolani, G. Seravalli, C. Villa, and M. Dallabora, "A new erasing method for a single-voltage long-endurance Flash memories," IEEE Electron Device Lett., vol. 19, pp. 37-39, Feb. 1998.
8. A. Chimenton, P. Pellati, and P. Olivo, "Constant charge erasing scheme for flash memories," IEEE Trans. Electron Devices, vol. 49, pp. 613-618, Apr. 2002.
9. _, "Analysis of erratic bits in flash memories," IEEE Trans. Device Mater. Rel., vol. 1, pp. 179-184, Dec. 2001.
10. T. Endoh, H. Iizuka, S. Aritome, R. Shirota, and F. Masuoka, "New write/erase operation tecnology for flash EEPROM cells to improve the read disturb characteristics," in IEDM Tech. Dig., 1992, pp. 603-606.
11. F. Nebel and M. Jourdain, "On the correlation between interface defects, positive oxide charge and hole fluence throughout the oxide," J. Non-Cryst. Solids, vol. 245, pp. 67-72, 1999.