A compact on-chip ECC for low cost flash memories

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 5, 1997, Pages 662-668

  Tanzawa, Toru ^a,c,d,e   Tanaka, Tomoharu ^a,c,f   Takeuchi, Ken ^a,c,g   Shirota, Riichiro ^a   Aritome, Seiichi ^a,h   Watanabe, Hiroshi ^a   Hemink, Gertjan ^b   Shimizu, Kazuhiro ^a   Sato, Shinji ^a   Takeuchi, Yuji ^a   Ohuchi, Kazunori ^a  

^a TOSHIBA CORPORATION   (Japan)

^b NXP SEMICONDUCTORS   (Netherlands)

^c Saitama University ^*

^d SAITAMA UNIVERSITY   (Japan)

^e TOHOKU UNIVERSITY   (Japan)

^f UNIVERSITY OF TSUKUBA   (Japan)

^g UNIVERSITY OF TOKYO   (Japan)

^h IEEE

Author keywords

Cumulative error rate; Flash memory; On chip ECC; Reliability improvement

Indexed keywords

BUFFER STORAGE; CELLULAR ARRAYS; ELECTRONICS PACKAGING; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; NAND CIRCUITS; POWER CONTROL;

CUMULATIVE SECTOR ERROR RATE; ERROR CORRECTING CIRCUITS (ECC); FLASH MEMORIES; SENSE AMPLIFIERS;

NONVOLATILE STORAGE;

EID: 0031146351     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.568829     Document Type: Article

References (14)

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