A 0.13-μm CMOS NOR flash memory experimental chip for 4-b/cell digital storage

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 131-134

  Micheloni, R ^a   Khouri, O ^a   Gregori, S ^b   Cabrini, A ^b   Campardo, G ^a   Fratin, L ^a   Torelli, G ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS TIME; CIRCUIT SOLUTION; CLOSED-LOOP; MOST SIGNIFICANT BIT; NOR FLASH MEMORY; SWITCHED CAPACITOR; VOLTAGE SENSING; WAVEFORM GENERATORS;

ANALOG TO DIGITAL CONVERSION; DIGITAL STORAGE;

FLASH MEMORY;

EID: 33646847344     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. M. Bauer, et al.: "A multilevel-cell 32-Mb flash memory", IEEE Int. Solid-State Circuits Conference Dig. Tech. Papers, Feb. 1995, pp. 132-133.
2. M. Pasotti, et al.: "Analog sense amplifiers for high density NOR Flash memories", Proc. IEEE Custom Integrated Circuits Conference, May 1999, pp. 334-335.
3. G. Campardo, et al.: "A 40mm2 3V 50MHz 64Mb 4-level cell NOR-type Flash memory", IEEE Int. Solid-State Circuits Conference Dig. Tech. Papers, Feb. 2000, pp. 274-275.
4. A. Pierin, et al.: "High-speed low-power sense comparator for multilevel Flash memories", Proc. IEEE Int. Conference on Electronics, Circuits, and Systems, Dec. 2000, pp. 759-763.
5. O. Khouri, et al.: "Program word-line voltage generator for multilevel Flash memories", Proc. IEEE Int. Conference on Electronics, Circuits and Systems, Dec. 2000, pp. 1030-1033.