A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 5, 2000, Pages 682-689

  Nobukata, Hiromi ^a  

^a SONY CORPORATION   (Japan)

Author keywords

0.67 mb s program throughput; Array ground line (agl); Background pattern dependency (bpd); Eight level nand flash memory; Incremental step pulse programming (ispp) start voltage; Optimized pulsewidth programming

Indexed keywords

EID: 0000027444     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.841491     Document Type: Article

References (7)

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