Design and implementation of error detection and correction circuitry for multilevel memory protection

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2002, Pages 89-95

  Polianskikh, Boris ^a   Zilic, Zeljko ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; DYNAMIC RANDOM ACCESS STORAGE; ERROR CORRECTION; ERROR DETECTION; RELIABILITY THEORY;

DOUBLE ERROR DETECTING; ERROR CORRECTING CODE; MULTI-LEVEL DYNAMIC RANDOM ACCESS MEMORY; MULTILEVEL MEMORY PROTECTION; SINGLE ERROR CORRECTING;

LOGIC DESIGN;

EID: 0036080075     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Fault-models and tests for a 2-bit-per-cell MLDRAM
2. Semiconductor file memory
3. A sense and restore technique for multilevel DRAM
4. An experimental 2-bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Application
5. A four-level storage 4-Gb DRAM