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Volumn 2, Issue , 2000, Pages 759-762

High-speed low-power sense comparator for multilevel Flash memories

Author keywords

Comparator; Flash memories; Multilevel; Sense amplifier; Sensing

Indexed keywords

CHARGE-PUMP; COMMON MODE RANGE; COMPARATOR; CURRENT DRAIN; FULLY DIFFERENTIAL; GAIN STAGES; HIGH VOLTAGE GENERATORS; HIGH-SPEED; HIGH-VOLTAGES; INPUT SIGNAL; LOW POWER; MULTILEVEL; MULTILEVEL FLASH MEMORY; OFFSET COMPENSATION; POWER CONSUMPTION; SENSE AMPLIFIER; SENSING; SIMULATION RESULT; SPEED REQUIREMENT; SUPPLY VOLTAGES; TWO STAGE; VOLTAGE COMPARATOR; VOLTAGE MULTIPLIERS;

EID: 4344597192     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2000.912988     Document Type: Conference Paper
Times cited : (6)

References (7)
  • 3
    • 0030291637 scopus 로고    scopus 로고
    • A 117-mm2 3.3V only 128Mb multilevel NAND Flash memory for mass storage applications
    • Nov.
    • T. S. Jung, Y.-J. Choi, K.-D. Suh, et al, "A 117-mm2 3.3V only 128Mb multilevel NAND Flash memory for mass storage applications", IEEE J. Solid-State Circuits, vol.SC-31, no.11, Nov. 1996, pp. 1575-1583.
    • (1996) IEEE J. Solid-State Circuits , vol.SC-31 , Issue.11 , pp. 1575-1583
    • Jung, T.S.1    Choi, Y.-J.2    Suh, K.-D.3
  • 4
    • 0030402010 scopus 로고    scopus 로고
    • A sixteen level scheme enabling 64 Mbit Flash memory using 16 Mbit technology
    • D. L. Kencke, et al, "A sixteen level scheme enabling 64 Mbit Flash memory using 16 Mbit technology", IEDM 1996 Tech. Dig., pp. 937-939.
    • IEDM 1996 Tech. Dig. , pp. 937-939
    • Kencke, D.L.1
  • 5
    • 0032679086 scopus 로고    scopus 로고
    • Mixed serial-parallel sensing scheme for a 64-Mbit 4-bit/cell factory-programmed OTP-ROM
    • Sept.
    • G. Torelli, A. Manstretta, R. Gastaldi, and P. Rolandi, "Mixed serial-parallel sensing scheme for a 64-Mbit 4-bit/cell factory-programmed OTP-ROM", Microelectronics Journal, vol.30, n. 9, Sept. 1999, pp. 875-886.
    • (1999) Microelectronics Journal , vol.30 , Issue.9 , pp. 875-886
    • Torelli, G.1    Manstretta, A.2    Gastaldi, R.3    Rolandi, P.4
  • 6
    • 0022738392 scopus 로고
    • A four-state EEPR'OM using floating-gate memory cells
    • June
    • C. Bleiker and H. Melchior, "A four-state EEPR'OM using floating-gate memory cells", IEEE J. Solid-State Circuits, vol.22, June 1987, pp. 460-463.
    • (1987) IEEE J. Solid-State Circuits , vol.22 , pp. 460-463
    • Bleiker, C.1    Melchior, H.2
  • 7
    • 0026996006 scopus 로고
    • Design techniques for high-speed, high-resolution comparators
    • Dec.
    • B. Razavi and B. A. Wooley, "Design techniques for high-speed, high-resolution comparators", IEEE J. Solid-State Circuits, vol.27, Dec. 1992, pp. 1916-1926.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , pp. 1916-1926
    • Razavi, B.1    Wooley, B.A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.