3.3V-only 16Mb flash memory with row-decoding scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 42-43

  Atsumi, Shigeru ^a   Umezawa, Akira ^a   Kuriyama, Masao ^a   Banba, Hironori ^a   Ohtsuka, Nobuaki ^a   Tomita, Naoto ^a   Iyama, Yumiko ^a   Miyaba, Takeshi ^a   Sudoh, Ryo ^a   Kamiya, Eiji ^a   Tanimoto, Masao ^a   Hiura, Yohei ^a   Araki, Yoshiko ^a   Sakagami, Eiji ^a   Arai, Norihisa ^a   et al , ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BUFFER CIRCUITS; CAPACITANCE; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; DECODING; DETECTOR CIRCUITS; REDUNDANCY;

DECODER CIRCUIT; FLASH MEMORY; MEMORY CELLS; ROW DECODING SCHEME; SENSE AMPLIFIER;

DIGITAL STORAGE;

EID: 0030085298     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)