A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 11, 1996, Pages 1584-1588

  Ohkawa, Masayoshi ^a,b,c   Sugawara, Hiroshi ^a,d   Sudo, Naoaki ^a,c,e,f   Tsukiji, Masaru ^a,g,h,i   Nakagawa, Ken Ichiro ^a,i,j   Kawata, Masato ^a,i,j   Oyama, Ken Ichi ^a,g   Takeshima, Toshio ^a   Ohya, Shuichi ^a  

^a NEC CORPORATION   (Japan)

^b TOKYO CITY UNIVERSITY   (Japan)

^c Info Commun E

^d UNIVERSITY OF TSUKUBA   (Japan)

^e SOPHIA UNIVERSITY   (Japan)

^f TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^g KYUSHU UNIVERSITY   (Japan)

^h ULSI Device Development Laboratories

ⁱ JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

^j UNIVERSITY OF TOKYO   (Japan)

more..

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER PROGRAMMING; LOGIC CIRCUITS; PARALLEL PROCESSING SYSTEMS; SEMICONDUCTOR DEVICE MANUFACTURE;

COMPACT MULTILEVEL SENSE AMPLIFIER; DRAIN VOLTAGE CONTROLLED MULTILEVEL PROGRAMMING; FLASH MEMORY; MEMORY CELL; PARALLEL MULTILEVEL VERIFY CIRCUIT;

SEMICONDUCTOR STORAGE;

EID: 0030288232     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/jssc.1996.542302     Document Type: Article

References (6)

1. M. Bauer et al., "A multilevel-cell 32 Mb flash memory," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 132-133.
2. G. J. Hemink et al., "Fast and accurate programming method for multi-level NAND EEPROM's," in Svmp. VLSI Technology, 1995, pp. 129-130.
3. K. Takeuchi et al., "A double-level-Vth select gate array architecture for multi-level NAND flash memories," in Symp. VLSI Circuits Dig. Tech. Papers, Feb. 1995, pp. 69-70.
4. T. Jung et al., "A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 32-33.
5. 2 die size 3.3 V 64 Mb flash memory with FN-NOR type 4-level cell," in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 36-37.
6. T. Takeshima et al., "A 3.3 V single-power-supply 64 Mb flash memory with dynamic bit-line latch (DBL) programming scheme," in ISSCC Dig. Tech. Papers. Feb. 1994, pp. 148-149.