Automatic generation of error control codes for computer applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 3, 1998, Pages 502-506

  Fummi, Franco ^a   Sciuto, Donatella ^a   Silvano, Cristina ^b  

^a POLITECNICO DI MILANO   (Italy)

^b UNIVERSITY OF BRESCIA   (Italy)

Author keywords

Computer memory systems; Error control codes; Memory reliability; VLSI architectures

Indexed keywords

BIT ERROR RATE; CODES (SYMBOLS); DATA REDUCTION; ERROR ANALYSIS; ERROR CORRECTION; ERROR DETECTION; MICROPROCESSOR CHIPS; RESPONSE TIME (COMPUTER SYSTEMS); VLSI CIRCUITS;

DOUBLE ERROR DETECTING (DED) CODES; ERROR CONTROL CODES (ECC); ODD-BIT-PER-BYTE ERROR CORRECTION (OBC); SINGLE BYTE ERROR DETECTING (SBD) CODES; SINGLE ERROR CORRECTING (SEC) CODES;

DATA STORAGE EQUIPMENT;

EID: 0032162980     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.711322     Document Type: Article

References (13)

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