Program schemes for multilevel flash memories

Proceedings of the IEEE

Volumn 91, Issue 4, 2003, Pages 594-601

  Grossi, Marco ^b   Lanzoni, Massimo ^b   Riccò, Bruno ^a,b,c  

^a IEEE   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c Italian Association of Electrical and Electronics Engineers   (Italy)

Author keywords

Flash; Memories; Multilevel; Programming

Indexed keywords

COMPUTER PROGRAMMING; DATA STORAGE EQUIPMENT; GATES (TRANSISTOR); LOGIC DESIGN; LOGIC GATES; PROGRAM PROCESSORS;

CHANNEL HOT ELECTRONS; CURRENT ABSORTION; MULTILEVELS; NARROWER THRESHOLD VOLTAGE DISTRIBUTIONS;

FLASH MEMORY;

EID: 3142694456     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2003.811714     Document Type: Review

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