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IEEE Transactions on Electron Devices

Volumn 48, Issue 9, 2001, Pages 2032-2042

Basic feasibility constraints for multilevel CHE-programmed flash memories

(3) Modelli, Alberto a Manstretta, Alessandro a Torelli, Guido b

a STMICROELECTRONICS (Italy)

b UNIVERSITY OF PAVIA (Italy)

Author keywords

Channel hot electron programming; Flash memories; Multilevel storage

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CONSTRAINT THEORY; DATA STORAGE EQUIPMENT; ELECTRONS; RELIABILITY;

CHANNEL HOT ELECTRON INJECTION; DATA RETENTION; PROGRAMMING ALGORITHMS; READ DISTURB IMMUNITY; SENSE CIRCUITRY SENSITIVITY;

FLASH MEMORY;

EID: 0035445243 PISSN: 00189383 EISSN: None Source Type: Journal
DOI: 10.1109/16.944193 Document Type: Article

Times cited : (20)

References (28)

1
- 0029253928
- A multilevel-cell 32 Mb flash memory
- 1995 IEEE Int. Solid-State Circuits Conf. Dig., San Francisco, CA, 1995 , pp. 132-133
- Bauer, M.¹ Alexis, R.² Atwood, G.³ Baltar, B.⁴ Fazio, A.⁵ Frary, K.⁶ Hensel, M.⁷ Ishac, M.⁸ Javanifard, J.⁹ Landgraf, M.¹⁰ Leak, D.¹¹ Loe, K.¹² Mills, D.¹³ Ruby, P.¹⁴ Rozman, R.¹⁵ Sweha, S.¹⁶ Talreja, S.¹⁷ Wojciechowski, K.¹⁸

2
- 0032304222
- Nonvolatile multilevel memories for digital applications
- Dec.
- (1998) Proc. IEEE , vol.86 , pp. 2399-2421
- Riccó, B.¹ Torelli, G.² Lanzoni, M.³ Manstretta, A.⁴ Maes, H.E.⁵ Montanari, D.⁶ Modelli, A.⁷

3
- 0003443760
- Binary and multilevel flash cells
- P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Eds. Norwell, MA: Kluwer; ch. 3
- (1999) Flash Memories
- Eitan, B.¹ Roy, A.²

4
- 0344108216
- Feasibility of multilevel storage in flash EEPROM cells
- Proc. Eur. Solid-State Device Res. Conf.'95, Bolgna, Italy, 1995 , pp. 213-216
- De Graaf, C.¹ Young, P.² Hulsbos, D.³

5
- 0030387349
- Multilevel flash cells and their trade-offs
- (1996) IEDM Tech. Dig. , pp. 169-172
- Eitan, B.¹ Kazerounian, R.² Roy, A.³ Crisenza, G.⁴ Cappelletti, P.⁵ Modelli, A.⁶

6

7
- 0030081176
- A 3.3 V 128 Mb multilevel NAND flash memory for mass storage applications
- 1996 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 1996 , pp. 32-33
- Jung, T.-S.¹ Choi, Y.-J.² Suh, K.-D.³ Suh, B.-H.⁴ Kim, J.-K.⁵ Lim, Y.-H.⁶ Koh, Y.-N.⁷ Park, J.-W.⁸ Lee, K.-J.⁹ Park, J.H.¹⁰ Park, K.-T.¹¹ Kim, J.-R.¹² Lee, J.-H.¹³ Lim, H.-K.¹⁴

8
- 0030083353
- 2 3.3 V 64 Mb flash memory with FN-NOR type 4-level cell
- 1996 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 1996 , pp. 36-37
- Ohkawa, M.¹ Sugawara, H.² Sudo, N.³ Tsukiji, M.⁴ Nakagawa, K.⁵ Kawata, M.⁶ Oyama, K.⁷ Takeshima, T.⁸ Ohya, S.⁹

9
- 0033221598
- A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications
- Nov.
- (1999) IEEE J. Solid-State Circuits , vol.34 , pp. 1544-1550
- Nozoe, A.¹ Kotani, H.² Tsujikawa, T.³ Yoshida, K.⁴ Furusawa, K.⁵ Kato, M.⁶ Nishimoto, T.⁷ Kume, H.⁸ Kurata, H.⁹ Miyamoto, N.¹⁰ Kubono, S.¹¹ Kanamitsu, M.¹² Koda, K.¹³ Nakayama, T.¹⁴ Kouro, Y.¹⁵ Hosogane, A.¹⁶ Ajika, N.¹⁷ Kobayashi, K.¹⁸

10
- 0000027444
- A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming
- May
- (2000) IEEE J. Solid-State Circuits , vol.35 , pp. 682-690
- Nobukata, H.¹ Takagi, S.² Hiraga, K.³ Ohgishi, T.⁴ Miyashita, M.⁵ Kamimura, K.⁶ Hiramatsu, S.⁷ Sakai, K.⁸ Ishida, T.⁹ Arakawa, H.¹⁰ Itoh, M.¹¹ Naiki, I.¹² Noda, M.¹³

11
- 0020844527
- An improved method for programming a word-erasable EEPROM
- Nov./Dec.
- (1983) Alta Freq. , vol.52 , pp. 487-494
- Torelli, G.¹ Lupi, P.²

12
- 0024752312
- A 90-ns one-million erase/program cycle 1-Mbit flash memory
- Oct.
- (1989) IEEE J. Solid-State Circuits , vol.24 , pp. 1259-1264
- Kynett, V.N.¹ Fandrich, M.L.² Anderson, J.³ Dix, P.⁴ Jungroth, O.⁵ Kreifels, J.A.⁶ Lodenquai, R.A.⁷ Vajdic, B.⁸ Wells, S.⁹ Winston, M.D.¹⁰ Yang, L.¹¹

13
- 0028538112
- A quick intelligent page-programming architecture and a shielding bitline sensing method for 3 V-only NAND flash memory
- Nov.
- (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 1366-1373
- Tanaka, T.¹ Tanaka, Y.² Nakamura, H.³ Sakui, K.⁴ Oodaira, H.⁵ Shirota, R.⁶ Ohuchi, K.⁷ Masuoka, F.⁸ Hara, H.⁹

14
- 0030358513
- Technological and design constraints for multilevel flash memories
- Proc. 3rd IEEE Int. Conf. Electronics, Circuits, and Systems, Rhodes, Greece, 1996 , pp. 1005-1008
- Calligaro, C.¹ Manstretta, A.² Modelli, A.³ Torelli, G.⁴

15
- 0003327790
- A new programming method and cell architecture for multi-level NAND flash memories
- 14th IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, CA, Aug. 1995
- Shirota, R.¹ Hemink, G.J.² Takeuchi, K.³ Nakamura, H.⁴ Aritome, S.⁵

16
- 0030680435
- Hot carrier self convergent programming method for multi-level flash cell memory
- Proc. 1997 Int. Reliability Physics Symp., Reno, NV, 1997 , pp. 104-109
- Candelier, P.¹ Mondon, F.² Guillaumot, B.³ Reinbold, G.⁴ Achard, H.⁵ Martin, F.⁶ Hartmann, J.⁷

17
- 0029255548
- A 34 Mb 3.3 V serial flash EEPROM for solid-state disk applications
- 1995 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 1995 , pp. 126-127
- Cernea, R.¹ Lee, D.J.² Mofidi, M.³ Chang, E.Y.⁴ Chien, W.-Y.⁵ Goh, L.⁶ Fong, Y.⁷ Yuan, J.H.⁸ Samachisa, G.⁹ Guterman, D.C.¹⁰ Mehrotra, S.¹¹ Sato, K.¹² Onishi, H.¹³ Ueda, K.¹⁴ Noro, F.¹⁵ Miyamoto, K.¹⁶ Morita, M.¹⁷ Umeda, K.¹⁸ Kubo, K.¹⁹

18
- 33749938628
- Comparison of current flash EEPROM erasing methods: Stability and how to control
- (1992) Int. Electron Devices Mag. 1992 Tech. Dig. , pp. 595-598
- Yoshikawa, K.¹ Yamada, S.² Miyamoto, J.³ Suzuki, T.⁴ Oshikiri, M.⁵ Obi, E.⁶ Hiura, Y.⁷ Yamada, K.⁸ Ohshima, Y.⁹ Atsumi, S.¹⁰

19
- 84954185679
- A self-convergence erasing scheme for a simple stacked gate flash EEPROM
- (1991) Int. Electron Devices Mag. 1991 Tech. Dig. , pp. 307-310
- Yamada, S.¹ Suzuki, T.² Obi, E.³ Oshikiri, M.⁴ Naruke, K.⁵ Wada, M.⁶

20
- 33747327940
- A novel erasing technology for 3.3 V flash memory with 64 Mb capacity and beyond
- (1992) Int. Electron Devices Mag. 1992 Tech. Dig. , pp. 607-610
- Oyama, K.¹ Shirai, H.² Kodama, N.³ Kanamori, K.⁴ Saitoh, K.⁵ Hisamune, Y.S.⁶ Okazawa, T.⁷

21
- 0029403785
- A convergence scheme for over-erased flash EEPROM's using substrate-bias-enhanced hot electron injection
- Nov.
- (1995) IEEE Electron Device Lett. , vol.16 , pp. 500-502
- Hu, C.Y.¹ Kencke, D.L.² Banerjee, S.K.³ Richart, R.⁴ Bandyopadhyay, B.⁵ Moore, B.⁶ Ibok, E.⁷ Garg, S.⁸

22
- 0024125531
- 2 films
- Dec.
- (1988) IEEE Trans. Electron Devices , vol.35 , pp. 2259-2267
- Olivo, P.¹ Nguyen, T.N.² Ricco, B.³

23
- 0027306901
- Novel read disturb failure mechanism induced by flash cycling
- (1993) Proc. 1993 Int. Reliability Physics Symp., Las Vegas , pp. 127-132
- Brand, A.¹ Wu, K.² Pan, S.³ Chin, D.⁴

24
- 0028755689
- Read-disturb degradation mechanism due to electron trapping in the tunnel oxide for low-voltage flash memories
- (1994) Int. Electron Devices Mag. 1994 Tech. Dig. , pp. 45-48
- Kato, M.¹ Miyamoto, N.² Kume, H.³ Satoh, A.⁴ Adachi, T.⁵ Ushiyama, M.⁶ Kimura, K.⁷

25
- 0029718243
- Non-uniform current flow through thin oxide after Fowler-Nordheim current stress
- (1996) Proc. 1996 Int. Reliability Physics Symp., San Diego, CA , pp. 108-112
- Yamada, S.¹ Amemiya, K.² Yamane, T.³ Hazama, H.⁴ Hashimoto, K.⁵

26
- 0016961262
- On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique
- June
- (1976) IEEE J. Solid-State Circuits , vol.11 SC , pp. 374-378
- Dickson, J.¹

27
- 0031210141
- A dynamic analysis of the Dickson charge pump circuit
- Aug.
- (1997) IEEE J. Solid-State Circuits , vol.32 , pp. 1231-1240
- Tanzawa, T.¹ Tanaka, T.²

28
- 0034297387
- Design of a sense circuit for low-voltage flash memories
- Oct.
- (2000) IEEE J. Solid-State Circuits , vol.35 , pp. 1415-1421
- Tanzawa, T.¹ Takano, Y.² Taura, T.³ Atsumi, S.⁴

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.