Modular architecture for a family of multilevel 256/192/128/64Mbit 2-bit/cell 3V-only NOR Flash memory devices

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2001, Pages 937-940

  Silvagni, Andrea ^a   Zanardi, Stefano ^a   Manstretta, Alessandro ^a   Scotti, Marco ^a   Crippa, Luca ^a   Ragone, Giancarlo ^a   Fusillo, Giuseppe ^a   Campardo, Giovanni ^a   Khouri, Osama ^b   Stefanelli, Marcello ^a  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

2-BIT/CELL; ASYNCHRONOUS ACCESS; BURST MODE; CMOS TECHNOLOGY; DEVICE ORGANIZATION; DIE SIZE; HIGH VOLTAGE; MODULAR ARCHITECTURES; NOR FLASH MEMORY;

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL;

FLASH MEMORY;

EID: 20444504862     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. M. Bauer, et al. "A multilevel-cell 32Mb flash memory", IEEE ISSCC Dig.Tech.Papers, Feb. 1995, pp 132-133.
2. P.Cappelletti, C. Golla, P. Olivo, E. Zanoni, "Flash memories"-Norwell, MA: Kluwer Academic Publishers, 1999.
3. B. Pviccò, et al. "Nonvolatile multilevel memories for digital applications", Proc. IEEE, vol. 86, pp. 2399-2421, Dec. 1998.
4. 2 3-V-Only 50-Mhz 64-Mb 2-b/cell CHE NOR Flash Memory", IEEE J. Solid-State Circuits, VOL. 35 No. 11 Nov. 2000, pp.1655-1667.
5. R. Micheloni, et al, "Hierarchical Sector Biasing Organization for Flash Memories", IEEE International Workshop MTDT 2000, San Jose, CA (USA).
6. O. Khouri, et al. "Program Word-line Voltage Generator for multilevel Flash memories", Proc. 2000 IEEE Int. Conf. on Electronics, Circuits and Systems (ICECS). pp. 1030-1033.