Stand-by low-power architecture in a 3V-only 2-bit/cell 64-Mbit flash memory

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2001, Pages 929-932

  Micheloni, Rino ^a   Motta, Ilaria ^a   Khouri, Osama ^b   Torelli, Guido ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

2-BIT/CELL; ACCESS TIME; ASYNCHRONOUS ACCESS; CHARGE PUMP; CURRENT CONSUMPTION; FLASH MEMORY DEVICES; LINE VOLTAGE; LOW POWER; LOW POWER ARCHITECTURE; MEMORY CHIPS; NORMAL OPERATIONS;

CHARGE PUMP CIRCUITS; ELECTRONIC EQUIPMENT; PUMPS; TRANSIENTS;

FLASH MEMORY;

EID: 33646848974     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. B. Riccò, et al. "Nonvolatile multilevel memories for digital applications", Proc. IEEE, vol. 86, no. 12, pp. 2399-2421, Dec. 1998.
2. J. Dickson, "On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique", IEEE J. Solid State Circuits, vol. SC-11, no. 3, pp. 374-378, June 1976.
3. O. Khouri, R. Micheloni, I. Motta, G. Torelli, "Word-line read voltage regulator with capacitive boosting for multimegabit multilevel Flash memories", Proc. European Conf. on Circuit Theory and Design, Aug.-Sept. 1999, pp. 145-148.
4. 2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR Flash memory", IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1655-1667, Nov. 2000.