Hierarchical sector biasing organization for flash memories

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 2000, Pages 29-33

  Micheloni, Rino ^a   Zammattio, Matteo ^a   Campardo, Giovanni ^a   Khouri, Osama ^b   Torelli, Guido ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; ELECTRIC POTENTIAL; ELECTRON MULTIPLIERS; GATES (TRANSISTOR); SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR QUANTUM WELLS;

FLASH MEMORY; HIERARCHICAL BIASING ARCHITECTURE;

SEMICONDUCTOR STORAGE;

EID: 0033697934     PISSN: 10874852     EISSN: None     Source Type: Journal    
DOI: 10.1109/MTDT.2000.868612     Document Type: Article

References (6)

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