A 4Gb 2b/cell NAND Flash memory with embedded 5b BCH ECC for 36MB/s system read throughput

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Micheloni, R ^a   Ravasio, R ^a   Marelli, A ^a   Alice, E ^a   Altieri, V ^a   Bovino, A ^a   Crippa, L ^a   Di Martino, E ^a   D'Onofrio, L ^a   Gambardella, A ^a   Grillea, E ^a   Guerra, G ^a   Kim, D ^b   Missiroli, C ^a   Motta, I ^a   Prisco, A ^a   Ragone, G ^a   Romano, M ^a   Sangalli, M ^a   Sauro, P ^a   Scotti, M ^a   Won, S ^b   more..

^a STMICROELECTRONICS   (Italy)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; ERROR ANALYSIS; FLASH MEMORY; NETWORK ARCHITECTURE;

CHIEN CIRCUITS; NAND FLASH MEMORY;

NAND CIRCUITS;

EID: 39749172648     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. D-S. Byeon, et al., "An 8Gb Multi-Level NAND Flash Memory with 63nm STI CMOS Process Technology," ISSCC Dig. Tech. Papers, pp. 46-47, Feb., 2005.
2. S. B. Wicker, Error Control Systems for Digital Communication and Storage, Prentice Hall, 1995.
3. S. Tanzawa, et al., "A Compact on-chip ECC for Low Cost Flash Memories," IEEE J. Solid-State Circuits, vol. 32, pp 662-669, May, 1997.