An error control code scheme for multilevel flash memories

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 2001, Pages 45-49

  Gregori, Stefano ^a   Khouri, Osama ^b   Micheloni, Rino ^b   Torelli, Guido ^a  

^a UNIVERSITY OF PAVIA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; DECODING; ENCODING (SYMBOLS); ERROR CORRECTION;

ERROR CONTROL CODE (ECC); MULTILEVEL FLASH MEMORIES;

PROM;

EID: 0034876224     PISSN: 10874852     EISSN: None     Source Type: Journal    
DOI: 10.1109/MTDT.2001.945227     Document Type: Article

References (8)

1. A multilevel-cell 32 Mb Flash memory
2. Nonvolatile multilevel memories for digital applications
3. Codes for error correction in high-speed memory systems - Part I: Correction of cell defects in integrated memories
4. An experimental large-capacity semiconductor file memory using 16-levels/cell storage
5. Construction of polyvalent error control codes for multilevel memories
6. The reliability of semiconductor RAM memories with on-chip error-correction codes
7. Dichotomic current-mode serial sensing methodology for multistorage non-volatile memories