Algorithm-based low-power and high-performance multimedia signal processing

Proceedings of the IEEE

Volumn 86, Issue 6, 1998, Pages 1155-1202

  Liu, K J Ray ^a   Wu, An Yeu ^b   Raghupathy, Arun ^a   Chen, Jie ^a  

^a UNIVERSITY OF MARYLAND   (United States)

^b NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

Adaptive filters; Discrete cosine transforms; FIR digital filters; IIR digital filters; Low power VLSI design; Motion estimation; Multirate processing; Parallel architectures; Reed Solomon codes; Video coding; Viterbi decoding

Indexed keywords

ADAPTIVE FILTERING; ALGORITHMS; COMPUTER ARCHITECTURE; DECODING; DIGITAL FILTERS; IMAGE ANALYSIS; IMAGE CODING; MATHEMATICAL TRANSFORMATIONS; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; VIDEO SIGNAL PROCESSING; VLSI CIRCUITS;

DISCRETE COSINE TRANSFORMS (DCT); MULTIMEDIA SIGNAL PROCESSING; REED SOLOMON CODES; VITERBI DECODING;

INTERACTIVE COMPUTER SYSTEMS;

EID: 0032097867     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.687834     Document Type: Article

References (172)

1. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design - A Systems Perspective, 2nd ed. Reading, MA: Addison-Wesley, 1993.
2. A. P. Chandrakasan, S. Sheng, and R. W. Broderscn, "Low-power CMOS digital design," IEEE J. Solid-Stale Circuits, vol. 27, pp. 473-484, Apr. 1992.
3. J. M. Rabaey, "Low power digital design," in Tutorials of the IEEE Int. Symposium on Circuits and Systems. London: IEEE Press, 1994, ch. 8, pp. 373-386.
4. G. M. Blair, "Designing low power digital CMOS," Electron. Commun. Eng. J., pp. 229-236, Oct. 1994.
5. Z. J. Leninios and K. J. Gabriel, "Low-power electronics," IEEE Design Test Comput. Mag., vol. 11, pp. 14-23, Winter 1994.
6. A. P. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, pp. 498-523, Apr. 1995.
7. D. Liu and C. Svensson, 'Trading speed for low power by choice of supply and threshold voltages," IEEE J. Solid-State Circuits, vol. 28, pp. 10-17, Jan. 1993.
8. A. Yoshino, K. Kumagai, S. Kurosawa, H. Itoh, and K. Okumura, "Design methodology for low-power, high-speed CMOS devices utilizing SOI technology," in Proc. IEEE Int. SOI Conf., Palm Springs, CA, Oct. 1993, pp. 170-171.
9. K. Hwang, Computer Arithmetic: Principles, Architecture, Design. New York: Wiley, 1979.
10. S. A. White, "Applications of distributed-arithmetic to digital signal processing: A tutorial review," IEEE Aconst., Speech, Signal Processing Mag., pp. 4-19, July 1989.
11. M. T. Sun, T. C. Chen, and A. M. Gottlieb, "VLSI implementation of a 16 × 16 discrete cosine transform," IEEE Trans. Circuits Syst., vol. 36, pp. 610-617, Apr. 1989.
12. C. T. Chiu and K. J. R. Liu, "Real-time parallel and fully pipelined two-dimensional DCT lattice structures with applications to HDTV systems," IEEE Trans. Circuits Syst. Video Teclmol., vol. 2, pp. 25-37, Mar. 1992.
13. V. Srinivasan and K. J. R. Liu, "VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video application," IEEE Trans. Circuits Syst. Video Teclmol., vol. 6, pp. 87-96, Feb. 1996.
14. F. J. Taylor, "Residue arithmetic: A tutorial with examples," IEEE Comput. Mag., pp. 50-62, May 1984.
15. M. A. Bayoumi, G. A. Jullien, and W. C. Miller, "A look-up table VLSI design methodology for RNS structures used in DSP applications," IEEE Trans. Circuits Syst., vol. 34, pp. 604-616, June 1987.
16. K. M. Elleithy and M. A. Bayoumi, "Fast and flexible architectures for RNS arithmetic decoding," IEEE Trans. Circuits Syst. II, vol. 39, pp. 226-235, Apr. 1992.
17. Y. C. Lim and S. R. Parker, "FIR filter design over a discrete power-of-two coefficient space," IEEE Trans. Acoust., Speech, Signal Processing, vol. 31, pp. 583-591, June 1983.
18. Y. C. Lim, "Design of discrete-coefficient-value linear phase FIR filters with optimum normalized peak ripple magnitude," IEEE Trans. Circuits Syst., vol. 37, pp. 1480-1486, Dec. 1990.
19. C.-K. Chen and J.-H. Lee, "Design of linear-phase quadrature mirror filters with power-of-two coefficients," IEEE Trans. Circuits Syst. I, vol. 41, pp. 445-156, July 1994.
20. J. Candy and G. Ternes, Oversampling Delta-Sigma Data Converters. New York: IEEE Press, 1991.
21. \V. C. Athas, L. Svensson, J. Koller, N. Tzartzanis, and E. Y.-C Chou, "Low-power digital systems based on adiabatic-switching principles," IEEE Trans. VLSI Syst., vol. 2, pp. 398-406, Dec. 1994.
22. K. Roy and S. C. Prasad, "Circuit activity based logic synthesis for low power reliable operations," IEEE Trans. VLSI Syst., vol. 1, pp. 503-513, Dec. 1993.
23. M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, "Prccomputation-based sequential logic optimization for low power," IEEE. Trans. VLSI Syst., vol. 2, pp. 426-436, Dec. 1994.
24. C.-L. Su, C.-Y. Tsui, and A. M. Despain, "Saving power in the control path of embedded processors," IEEE Design Test Comput. Mag., vol. 11, pp. 24-30, Winter 1994.
25. L. Benini, P. Siegel, and G. D. Micheli, "Saving power by synthesizing gated clocks for sequential circuits," IEEE Design Test Comput. Mag., vol. 11, pp. 32-41, Winter 1994.
26. S. Gary, P. Ippolito, G. Gerosa, C. Dietz, J. Eno, and H. Sanchez, "PowerPC 603, a microprocessor for portable computers," IEEE Design Test Coinpiit. Mag., vol. 11, pp. 14-23, Winter 1994.
27. S. A. Khan and V. K. Madisetti, "System partitioning of MCM for low power," IEEE Design Test Coinpiit. Alç., vol. 12, pp. 41-52, Spring 1995.
28. T. Koga, K. linuma, A. Hirano, Y. lijima, and T. Ishiguro, "Motion-compensated interframe coding for video conferencing," in Proc. National Telecoininun. Conf., New Orleans, LA, 1981, pp. G531-G535.
29. J. R. Jain and A. K. Jain, "Displacement measurement and its application in interframe imace codina," IEEE Trans. Commun., vol. COM-29, pp. 1799-1808, Dec. 1981.
30. A.-Y. Wu and K. J. R. Liu, "Split recursive least-squares: Algorithms, architectures, and applications," IEEE Trans. Circuits Syst. If, vol. 43, pp. 645-658, Sept. 1996.
31. S. H. Nawab, A. Oppenheim, A. P. Chandrakasan, J. M. Winograd, and J. T. Ludwig, "Approximate signal processing," J. VLSI Signal Processing, vol. 15, pp. 177-200, Jan. 1997.
32. L. R. Rabiner and R. W. Schäfer, Digital Processing of Speech Signals. Englewood Cliffs, NJ: Prentice-Hall, 1978.
33. H. Li, A. Lundmark, and R. Forchheimer, "Image sequence coding at very low bitrates: A review," IEEE Trans. linage Processing, vol. 3, pp. 589-609, Sept. 1994.
34. A. V. Oppenheim and H. Nawab, Symbolic anil Knowledge Based Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1992.
35. T. H. Meng, R. Broderson, and D. Messerschmitt, "Asynchronous design for programmable digital signal processors," IEEE Trans. Signal Processing, vol. 39, pp. 939-952, Apr. 1991.
36. K. J. R. Liu, S.-F. Hsieh, and K. Yao, "Systolic block householder transformation for RLS algorithm with two-level pipelined implementation," IEEE Trans. Acoiist.. Speech, Signal Processing, vol. 40, pp. 946-958, Apr. 1992.
37. C.-L. Wang, "Bit-serial VLSI implementation of delayed LMS adaptive FIR filter," IEEE Trans. Signal Processing, vol. 42, pp. 2169-2175, Aug. 1994.
38. A. V. Oppenheim and R. W. Schafer, Discrete-rune Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1989.
39. K. K. Parhi and D. G. Messerschmitt, "Pipeline interleaving and parallelism in recursive digital filters-Part I: Pipelining using scattered look-ahead and decomposition," IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 1099-1117, July 1989.
40. __, "Pipeline interleaving and parallelism in recursive digital filters-Part II: Pipelined incremental block filtering," IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 1118-1134, July 1989.
41. K. K. Parhi, "High-level algorithm and architecture transformations for DSP synthesis," J. VLSI Signal Processing, vol. 9, pp. 121-143, Jan. 1995.
42. N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filler. Norwell, MA: Kluwer, 1994.
43. P. P. Vaidyanathan, Multirale Systems and Filter Banks. Englewood Cliffs, NJ: Prentice-Hall, 1993.
44. K. J. R. Liu and C. T. Chiu, "Unified parallel lattice structures for time-recursive discrete cosine/sine/Hartley transforms," IEEE Trans. Signal Processing, vol. 41, pp. 1357-1377, Mar. 1993.
45. K. J. R. Liu, C. T. Chiu, R. K. Kolagotla, and J. F. Jaja', "Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transforms," IEEE Trans. Circuits Syst. Video Techno!., vol. 4, pp. 168-180, Apr. 1994.
46. U.-V. Koc and K. J. R. Liu, "Discrete-cosine/sine-transform based motion estimation," in Proc. IEEE Int. Conf. Image Processing, Austin, TX, Nov. 1994, vol. 3, pp. 771-775.
47. __, "DCT-based subpixel motion estimation," in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Processing, Atlanta, G A, 1996, pp. 1930-1933.
48. Y. H. Hu, "CORDIC-based VLSI architectures for digital signal processing," IEEE Signal Processing Mag., pp. 16-35, July 1992.
49. G. Fettweis and H. Meyr, "Parallel Viterbi algorithm implementation: Breaking the ACS-bottleneck," IEEE Trans. Commun., vol. 37, pp. 785-789, Aug. 1989.
50. H.-D. Lin and D. G. Messerschmitt, "Algorithms and architectures for concurrent Viterbi decoding," in Proc. IEEE Int. Conf. Communications, 1989, pp. 836-840.
51. H. K. Thapar and J. Cioffi, "A block processing method for designing high speed Viterbi decoders," in Proc. IEEE Communications Conf., June 1989, pp. 1096-1100.
52. G. Long, F. Ling, and J. G. Proakis, "The LMS algorithm with delayed coefficient adaptation," IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 1397-1405, Sept. 1989.
53. T. H. Meng and D. G. Messerschmitt, "Arbitrarily high sampling rate adaptive filtering," IEEE Trans. Acoust.. Speech, Signal Processing, vol. ASSP-35, pp. 455-70, Apr. 1987.
54. A.-Y. Wu, K. J. R. Liu, Z. Zhang, K. Nakajima, A. Raghupathy, and S.-C. Liu, "Algorithm-based low power DSP design: Methodology and verification," in VLSI Signal Processing VIII, T. Nishitani and K. K. Parhi, Eds. New York: IEEE Press, 1995, pp. 277-286.
55. H. K. Kwan and M. T. Tsim, "High speed 1-D FIR digital filtering architectures using polynomial convolution," in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Processing, Dallas, TX, Apr. 1987, pp. 1863-1866.
56. Z.-J. Mou and P. Duhamel, "Short-length FIR filters and their use in fast nonrecursive filtering," IEEE Trans. Signal Processing, vol. 39, pp. 1322-1332, June 1991.
57. J. D. Johnston, "A filter family designed for use in quadrature mirror filter banks," in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Processing, 1980, pp. 291-294.
58. Y. Nakamura, K. Oguri, and A. Nagoya, "Synthesis from pure behavioral descriptions," in High-Level VLSI Synthesis, R. Camposano and \V. Wolf, Eds.. Norwell, MA: Kluwer, 1991, pp. 205-229.
59. A.-Y. Wu, K. Liu, Z. Zhang, K. Nakajima, and A. Raghupathy, "Low-power design methodology for DSP systems using multirate approach," in Proc. IEEE Int. Symp. Circuits and Systems, Atlanta, GA, May 1996, pp. IV.292-295.
60. E. Frantzeskakis, J. S. Baras, and K. J. R. Liu, 'Time-recursive computation and real-time parallel architectures: A framework," IEEE Trans. Signal Processing, vol. 43, pp. 2762-2775, Nov. 1995.
61. H. S. Hou, "A fast recursive algorithm for computing the discrete cosine transform," IEEE Trans. Acoust. Speech, Signal Processing, vol. 35, pp. 1455-1461, Oct. 1987.
62. B. G. Lee, "A new algorithm to compute the discrete cosine transform," IEEE Trans. Acoust. Speech, Signal Processing, vol. 32, pp. 1243-1245, Dec. 1984.
63. A.-Y. Wu and K. J. R. Liu, "Algorithm-based low-power transform coding architectures: The multirate approach," IEEE Trans. VLSI Syst., to be published.
64. K. Konstantinides, "Fast subband filtering in MPEG audio coding," IEEE Signal Processing Lett., vol. 1, pp. 26-28, Feb. 1994.
65. A.-Y. Wu and K. J. R. Liu, "A low-power and low-complexity DCT/IDCT VLSI architecture based on backward Chebyshev recursion," in Proc. IEEE Int. Symp. Circuits and Systems, London, England, May 1994, pp. IV.155-158. .
66. A. N. Skodras, "Fast discrete cosine transform pruning," IEEE Trans. Signal Processing, vol. 42, pp. 1833-1837, July 1994.
67. H. S. Malvar, "Lapped transforms for efficient transform/subband coding," IEEE Trans. Acoust., Speech, Signal Processing, vol. 38, pp. 969-978, June 1990.
68. __, "Extended lapped transforms: Properties, applications, and fast algorithms," IEEE Trans. Signal Processing, vol. 40, pp. 2703-2714, Nov. 1992.
69. H. S. Malvar and D. H. Staelin, 'The LOT: Transform coding without blocking effects," IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 553-559, Apr. 1989.
70. E. Frantzeskakis, J. S. Baras, and K. J. R. Liu, 'Time-recursive computation and real-time parallel architectures with application on the modulated lapped transform," in Proc. SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations IV, San Diego, CA, July 1993, pp. 100-111.
71. H. S. Malvar, "Fast algorithm for modulated lapped transform," Electron. Lett., vol. 27, pp. 775-776, Apr. 1991.
72. H. Chiang and J. Liu, "Regressive implementations for the forward and inverse MDCT in MPEG audio coding," IEEE Signal Processing Lett., pp. 116-118, Apr. 1996.
73. Z. Wang, "Fast algorithms for the discrete II' transform and for the discrete Fourier transform," IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-32, pp. 803-816, Aug. 1984.
74. P. Pirsch, N. Demassieux, and W. Gehrke, "VLSI architectures for video compression-A survey," Proc. IEEE, vol. 83, pp. 220-245, Feb. 1995.
75. E. Petajan and J. Mailhot, "Grand alliance (HDTV) system" Proc. SP1E, San Jose, CA, 1994, pp. 2-15
76. L. Chiariglione, 'The MPEG and multimedia communications " IEEE Trans. Circuits Syst. Video Tecluwl., vol. 7, pp. 5-18 Feh 1997.
77. G. Karlsson, "Asynchronous transfer of video," IEEE Commun Mag., vol. 36, pp. 118-126, Aug. 1996.
78. R. Srinivasan and K. R. Rao, "Motion compensating coder for video conferencing," IEEE Trans. Commun., vol. COM-33 pn 888-896, Aug. 1985.
79. K. M. Yang, M. T. Sun, and L. Wu, "A family of VLSI designs for the motion compensation block-matching algorithm," IEEE Trans. Circuits Syst., vol. 36, pp. 1317-1325, Oct. 1989.
80. T. Komarek and P. Pirsch, "Array architectures for blockmatching algorithm," IEEE Trans. Circuits Syst., vol. 36 pp 1301-1308, Oct. 1989.
81. L. D. Vos and M. Stegherr, "Parameterizable VLSI architectures for the full-search block-matching algorithm," IEEE Trans Circuits Syst., vol. 36, pp. 1309-1316, Oct. 1989.
82. H.-M. Jong, L.-G. Chen, and T.-D. Chiueh, "Parallel architectures of 3-step search block-matching algorithms for video coding," in Proc. IEEE Int. Symp. Circuits and Systems, 1994 pp. 209-212.
83. G. Gupta and C. Chakrabarti, "VLSI architecture for hierarchical block matching," in Proc. IEEE Int. Symp. Circuits and Systems, 1994, pp. 215-218.
84. S. B. Pan, S. S. Chae, and R. H. Park, "VLSI architectures for block matching algorithms using systolic array," IEEE Trans. Circuits Syst. Video Tecluwl., vol. 6, pp. 67-73, Feb. 1996.
85. S. Dutta and W. Wolf, "A flexible parallel architecture adapted to block-matching motion-estimation algorithms," IEEE Trans. Circuits Syst. Video Tecluwl., vol. 6, pp. 74-86, Feb. 1996.
86. R. W. Young and N. G. Kihgsbury, "Frequency-domain motion estimation using a complex lapped transform," IEEE Trans. Image Processing, vol. 2, pp. 2-17, Jan. 1993.
87. A. N. Netravali and J. D. Robbins, "Motion compensated television coding-Part l," Bell Syst. Tecli. J., vol. 58, pp. 631-670, Mar. 1979.
88. J. D. Robbins and A. N. Netravali, "Recursive motion compensation: A review," in Image Sequence Processing and Dynamic Scene Analysis, T. S. Huang, Ed. Berlin, Germany: SpringerVerlag, 1983, pp. 76-103.
89. R. C. Kirn and S. U. Lee, "A VLSI architecture for a pel recursive motion estimation algorithm," IEEE Trans. Circuits Syst., vol. 36, pp. 1291-1300, Oct. 1989.
90. A. Singh, Optic Flow Computation-A Unified Perspective. New York: IEEE Computer Society Press, 1991.
91. A. Kojima, N. Sakurai, and J. Kishigami, "Motion detection using 3D-FFT spectrum," in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Processing, Minneapolis, MN, Apr. 1993, pp. V213-V216.
92. K. R. Rao and J. J. Hwang, Techniques and Standards for Image, Video, and Audio Coding. Englewood Cliffs, NJ: Prentice-Hall, 1994.
93. B. Girod, Motion Compensation: Visual Aspects, Accuracy, and Fundamental Limits. Norwell, MA: Kluwer, 1993.
94. S.-I. Uramoto, A. Takabatake, and M. Yoshimoto, "A halfpel precision motion estimation processor for NTSC-resolution video," IEICE Trans. Electronics, vol. 77, p. 1930, Dec. 1994.
95. K. Ishihara, S. Masuda, S. Hattori, H. Nishikawa, Y. Ajioka, T. Yamada, H. Amishiro, S. Uramoto, M. Yoshimoto, and T. Sumi, "A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search," IEEE J. Solid-Slate Circuits, vol. 30, pp. 1502-1509, Dec. 1995.
96. B. Girod, "Motion-compensating prediction with fractional-pel accuracy," IEEE Trans. Commun., vol. 41, p. 604, Apr. 1993.
97. K. K. Parhi, C.-Y. Wang, and A. P. Brown, "Synthesis of control circuits in folded pipelined DSP architectures," IEEE J. Solid-State Circuits, vol. 27, pp. 29-43, Jan. 1992.
98. J. Chen and K. J. R. Liu, "A complete pipelined parallel CORDIC architecture for motion estimation," in Proc. IEEE Int. Symp. Circuits and Systems, Hong Kong, 1997, pp. 2801-2804.
99. J. Chen and K. J. R. Liu, "A fully pipelined parallel CORDIC architecture for half-pel motion estimation," in Proc. IEEE Int. Conf. Image Processing, Santa Barbara, CA, Oct. 1997, vol. 2, pp. 574-577.
100. K. Hasegawa, K. Ohara, A. Oka, T. Kamada, Y. Nagaoka, K. Yano, E. Yamauchi, T. Kashiro, and T. Nakagawa, "Low-power I video encoder/decoder chip set for digital VCR's," IEEE J. Solid-State Circuits, vol. 31, pp. 1780-1788, Nov. 1996.
101. R. Li, B. Zeng, and M. L. Liou, "A new three-step search algorithm for block motion estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 4, pp. 438-442, Aug. 1994.
102. K. R. Rao and P. Tip, Discrete Cosine Transform: Algorithms, Advantages, and Applications. New York: Academic, 1990.
103. N. I. Cho and S. U. Lee, "DCT algorithms for VLSI parallel implementations," IEEE Trans. Acoust., Speech, Signal Processing, vol. 38, pp. 1899-1908, Dec. 1989.
104. L. W. Chang and M. C. Wu, "A unified systolic array for discrete cosine and sine transforms," IEEE Trans. Signal Processing, vol. 39, pp. 192-194, Jan. 1991.
105. S. Whitaker, J. Canaris, and K. Cameron, "Reed Solomon VLSI codec for advanced television," IEEE Trans. Circuits Syst. Video Technol., vol. 1, pp. 230-236, June 1991.
106. [ 106] S. B. Wicker, Error Control Systems for Digital Communication and Storage. Englewood Cliffs, NJ: Prentice-Hall, 1995.
107. T. S. Rappaport, Wireless Communications. New York: IEEE Press, 1996.
108. K. Maxwell, "Asymmetric digital subscriber line," IEEE Commun. Mag., vol. 34, pp. 100-107, Oct. 1996.
109. J. B. Cain and D. N. McGregor, "A recommended error control architecture for ATM networks with wireless links," IEEE J. Select. Areas Commun., vol. 15, pp. 16-27, Jan. 1997.
110. I. S. Reed and G. Solomon, "Reed-Solomon codes: A historical overview," in Reed Solomon Codes and Their Applications, S. P. Wicker and V. K. Bhargava, Eds. New York: IEEE Press, 1991, pp. 1-16.
111. [Ill] E. R. Berlekamp, Algebraic Coding Theory. New York: McGraw-Hill, 1968.
112. J. L. Massey, "Shift register synthesis and BCH coding," IEEE Trans. Inform. Theory, vol. IT-15, pp. 122-127, Jan. 1969.
113. Y. Sugiyama, M. Kasahara, S. Hirasawa, and T. Namekawa, "A method for solving key equation for decoding Goppa codes," Inform. Control, vol. 27, pp. 87-99, 1975.
114. G. D. Forney, Jr., "On decoding BCH codes," IEEE Trans. Inform. Theory, vol. IT-11, pp. 549-557, Oct. 1965.
115. R. E. Blahut, Algebraic Methods for Signal Processing and Error Control Coding. Berlin, Germany: Springer-Verlag, 1992.
116. Y. R. Shayan, T. Le-Ngoc, and V. K. Bhargava, "A versatile time domain Reed-Solomon decoder," IEEE J. Select. Areas Commun., vol. 8, pp. 1535-1542, Oct. 1990.
117. K. Y. Liu, "Architecture for VLSI design of Reed-Solomon decoders," IEEE Trans. Comput., vol. C-33, pp. 178-189, Feb. 1984.
118. H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen, and I. S. Reed, "A VLSI design of a pipeline Reed-Solomon decoder," IEEE Trans. Comput., vol. C-34, pp. 393-402, May 1985.
119. N. Demassieux, F. Jutand, and M. Muller, "A 10 MHz (255, 233) Reed-Solomon decoder," in Proc. IEEE Custom Integrated Circuits COM/, 1988, pp. 1761-1764.
120. H. M. Shao and I. S. Reed, "On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays," IEEE Trans. Comput., vol. 37, pp. 1273-1280, Oct. 1988.
121. P. Tong, "A 40 MHz encoder-decoder chip generated by a ReedSolomon code compiler," in Proc. Custom Integrated Circuits Conf., Boston, MA, May 1990, pp. 1351-1354.
122. E. Berlekamp, G. Seroussi, and P. Tong, "A hypersystolic (Reed-Solomon) decoder," in Reed Solomon Codes and Their Applications, S. P. Wicker and V. K. Bhargava, Eds. New York: IEEE Press, 1991, pp. 205-241.
123. R. P. Brent and H. T. Kung, "Systolic VLSI arrays for polynomial GCD computation," IEEE Trans. Comput., vol. C-33, pp. 731-736, Aug. 1984.
124. A. Raghupathy and K. J. R. Liu, "Low power/high speed design of a Reed Solomon decoder," in Proc. IEEE Int. Symp. Circuits and Systems, Hong Kong, June 1997, pp. 2060-2063.
125. D.-I. Oh, Y. Kirn, and S.-Y. Hwang, "A VLSI architecture of the trellis decoder block for the digital HDTV grand alliance system," lEEETrans. Consumer Electron., vol. 42, pp. 346-356, Aug. 1996.
126. I. Kang and A. Willson, Jr., "A low-power state-sequential Viterbi decoder for CDMA digital cellular applications," in Proc. IEEE Int. Symp. Circuits and Systems, May 1996, pp. 272-275.
127. C. B. Shung, P. H. Siegel, H. K. Thapar, and R. Karabed, "A 30 MHz trellis codec chip for partial-response channels," IEEE
128. J. Solid-State Circuits, vol. 26, pp. 1981-1987, Dec. 1991.
129. H. Dawid, G. Fettweis, and H. Meyr, "A CMOS 1C for Gb/s Viterbi decoding: System design and VLSI implementation," IEEE Trans. VLSI Sysl., vol. 4, pp. 17-31, Mar. 1996.
130. G. Feygin, P. Chow, P. G. Gulak, J. Chappel, G. Goodes, O. Hall, A. Sayes, S. Singh, M. B. Smith, and S. Wilton, "A VLSI implementation of a cascade Viterbi decoder with traceback," in Proc. IEEE Int. Symp. Circuits and Systems, May 1993, pp. 1945-1948.
131. P. J. Black and T. H. Meng, "A unified approach to the Viterbi algorithm state metric update for shift register processes," in Proc. IEEE Int. Conf. Acoust. Speech, Signal Processing, Mar. 1992. pp. V.629-V.632.
132. __, "Hybrid survivor path architectures for Viterbi decoders," in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Processing, 1993. pp. I.433-I.436.
133. C. M. Rader, "Memory management in a Viterbi decoder," IEEE Trans. Commun., vol. COM-29, pp. 1399-1401, Sept. 1981.
134. R. Cypher and C. B. Shung, "Generalized traceback techniques for survivor memory management in the Viterbi algorithm," in Proc. IEEE Global Telecommunications Conf., Dec. 1990, pp. 1318-1322.
135. M. Boo, R Arguello, J. D. Bruguera, R. Doallo, and E. L. Zapata, "High-performance VLSI architecture for the Viterbi algorithm," IEEE Trans. Commun., vol. 45, pp. 168-176, Feb. 1997.
136. P. J. Black and T. H. Meng, "A 140-Mb/s, 32-state, radix4 Viterbi decoder," IEEE J. Solid-Stale Circuits, vol. 27, pp. 1877-1885, Dec. 1992.
137. P. G. Gulak and T. Kailath, "Locally connected VLSI architectures for the Viterbi algorithm," 1EEEJ. Select. Areas Commun., vol. 6, pp. 527-537, Apr. 1988.
138. H.-D. Lin, B. Shung, and D. G. Messerschmitt, "Viterbi decoders for convolutional codes," in VLSI Signal Processing IV. New York: IEEE Press, 1990, pp. 381-391.
139. C. B. Shung, H. D. Lin, R. Cypher, P. H. Siegel, and H. K. Thapar, "Area-efficient architectures for the Viterbi algorithm-Part I: Theory," IEEE Trans. Commun., vol. 41, pp. 636-643, Apr. 1993.
140. _, "Area-efficient architectures for the Viterbi algorithm-Part II: Applications," IEEE Trans. Commun., vol. 41, pp. 802-807, May 1993.
141. F. Daneshgaran and K. Yao, 'The iterative collapse algorithm: A novel approach for the design of long constraint length Viterbi decoders-Part I," IEEE Trans. Commun., vol. 43, pp. 1409-1418, Feb. 1995.
142. H.-L. Li and C. Chakrabarti, "A new architecture for the Viterbi decoder for code rate k/n," IEEE Trans. Commun., vol. 44, pp. 158-164, Feb. 1996.
143. T. Ishitani, K. Kansho, N. Miyahara, S. Kubota, and S. Kalo, "A scarce-state-transition Viterbi-decoder VLSI for bit error correction," IEEEJ. Solid-State Circuits, vol. SC-22, pp. 575-581, Aug. 1987.
144. S. Kubota, S. Kato, and T. Ishitani, "Novel Viterbi decoder VLSI implementation and its performance," IEEE Trans. Commun., vol. 41, pp. 1170-1178, Aug. 1993.
145. J. B. Cain, G. C. Clark, and J. M. Geist, "Punctured convolutional codes of rate (n -1)/n and simplified maximum likelihood decoding," IEEE Trans. Inform. Theory, vol. IT-25, pp. 97-100, Jan. 1979.
146. G. Fettweis and H. Meyr, "High speed Viterbi processor: A systolic array solution," IEEEJ. Select. Areas Commun., vol. 8, pp. 1520-1533, Oct. 1990.
147. __, "High-speed parallel Viterbi decoding: Algorithm and VLSI-architecture," IEEE Commun. Mag., pp. 46-55, May 1989.
148. G.-H. Im, D. B. Harman, G. Huang, A. V. Mandzik, M. H. Nguyen, and J.-J. Werner, "51.84 Mb/s 16-CAP ATM LAN standard," IEEEJ. Select. Areas Commun., vol. 13, pp. 620-632, May 1995.
149. G.-H. Im and J.-J. Werner, "Bandwidth-efficient digital transmission over unshielded twisted-pair wiring," IEEE J. Select. Areas Commun., vol. 13, pp. 1643-1655, Dec. 1995.
150. J. S. Chow, J. C. Tu, and J. M. Cioffi, "A discrete multitone transceiver system for HDSL applications," IEEE J. Select. Areas Commun., vol. 9, pp. 895-909, Aug. 1991.
151. M. Ho, J. M. Cioffi, and J. A. C. Bingham, "Discrete mul-titone echo cancellation," IEEE Trans. Commun., vol. 44, pp. 817-825, July 1996.
152. J. G. Proakis, "Adaptive equalization for TDMA digital mobile radio," IEEE Trans. Veh. Teclmol., vol. 40, pp. 333-341, May 1991.
153. S. U. H. Qureshi, "Adaptive equalization," Proc. IEEE, vol. 73, pp. 1349-1387, Sept. 1985.
154. S. Haykin, Adaptive Filter Theory, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 1991.
155. C. S. H. Wong, J. C. Rudell, G. T. Uehara, and P. R. Gray, "A 50 MHz eight-tap adaptive equalizer for partial-response channels," IEEE J. Solid-Stale Circuits, vol. 30, pp. 228-233, Mar. 1995.
156. G. Cherubini, S. Olcer, and G. Ungerboeck, "A quaternary partial-response class-IV transceiver for 125 Mbit/s data transmission over unshielded twisted-pair cables: Principles of operation and VLSI realization," IEEE J. Select. Areas Commun., vol. 13, pp. 1656-1669, Dec. 1995.
157. R. S. Kajlcy, P. J. Hurst, and J. E. C. Brown, "A mixed-signal decision-feedback equalizer that uses a look-ahead architecture," IEEE J. Solid-State Circuits, vol. 32, pp. 450-459, Mar. 1997.
158. F. Lu and H. Samueli, "A 60 MBd, 480-Mb/s, 256-QAM decision-feedback equalizer in 1.2 /nil CMOS," IEEE J. SolidState Circuits, vol. 28, pp. 330-338, Mar. 1993.
159. E. D. Man, M. Schulz, R. Schmidmaier, M. Schobinger, and T. G. Noll, "Architecture and circuit design of a 6-GOPS signal processor for QAM demodulator applications," IEEE J. Solid-State Circuits, vol. 30, pp. 219-226, Mar. 1995.
160. H. Samueli, B. Daneshrad, R. B. Joshi, B. C. Wong, and H. T. Nicholas, "A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1Q HDSL transceivers," IEEE J. Select. Areas Commun., vol. 9, pp. 839-847, Aug. 1991.
161. J. H. Shynk, "Frequency-domain and multirate adaptive filtering," IEEE Signal Processing Mag., pp. 14-37, Jan. 1992.
162. C. Leiserson and J. Saxe, "Optimizing synchronous systems," J. VLSI Comput. Syst., vol. 1, no. 1, pp. 41-67, 1983.
163. G. Long, F. Ling, and J. G. Proakis, "Corrections to 'the LMS algorithm with delayed coefficient adaptation,'" IEEE Trans. Acoiist., Speech, Signal Processing, vol. 40, pp. 230-232, Jan. 1992.
164. M. Goel and N. R. Shanbhag, "Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN," IEEE Trans. Signal Processing, vol. 45, pp. 1276-1290, May 1997.
165. I. D. Yun and S. U. Lee, "On the fixed-point-error analysis of several fast DCT algorithms," IEEE Trans. Circuits Syst. Video Teclmol., vol. 3, pp. 27-41, Feb. 1993.
166. P. P. Vaidyanathan and P.-Q. Hoang, "Lattice structures for optimal design and robust implementation of two-channel perfectreconstruction QMF banks," IEEE Trans. Acoiist., Speech, Signal Processing, vol. 36, pp. 81-94, Jan. 1988.
167. I. K. Proudler, J. G. McWhirter, and T. J. Shepherd, "Computationally efficient QR decomposition approach to least squares adaptive filtering," Proc. Inst. Elect. Eng., vol. 138, pt. F, pp. 341-353, Aug. 1991.
168. H. M. Ahmed, "Alternative arithmetic unit architectures for VLSI digital signal processors," in VLSI and Modem Signal Processing, S. Y. Kung, H. J. Whitehouse, and T. Kailath, Eds. Englewood Cliffs, NJ: Prentice-Hall, 1986, ch. 16, pp. 277-303.
169. J.-H. Hsiao, L.-G. Chen, T.-D. Chiueh, and C.-T. Chen, "High throughput CORDIC-based systolic array design for the discrete cosine transform," IEEE Trans. Circuits Syst. Video Teclmol., vol. 5, pp. 218-225, June 1995.
170. S. MoIIoy, B. Schoner, A. Madisetti, R. Jain, and R. Matic, "An algorithm-driven processor design for video compression," in Proc. IEEE Int. Conf. Image Processing, Austin, TX, 1994, pp. 111.611-615.
171. A.-Y. Wu, K. J. R. Liu, and A. Raghupathy, "System architecture of an adaptive reconfigurable DSP computing engine," IEEE Trans. Circuits Syst. Video Teclmol., to be published.
172. L. B. Jackson, Digital Filters and Signal Processing, 2nd ed. Norwell, MA: Kluwer, 1989.