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Volumn , Issue , 1996, Pages 240-241
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Impact of cell threshold voltage distribution in the array of flash memories on scaled and multilevel flash cell design
a
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Author keywords
[No Author keywords available]
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Indexed keywords
CALCULATIONS;
COMPUTER PROGRAMMING;
CURRENT VOLTAGE CHARACTERISTICS;
ELECTRON TUNNELING;
FERMI LEVEL;
GATES (TRANSISTOR);
LEAKAGE CURRENTS;
OPTIMIZATION;
STATISTICAL METHODS;
BAND TO BAND TUNNELING;
BITLINE SEGMENTATION;
CELL THRESHOLD VOLTAGE DISTRIBUTION;
CHARGE PUMP CIRCUITRY FAILURE;
DRAIN INDUCED BARRIER LOWERING EFFECT;
FLASH MEMORIES;
FLOATING GATE VOLTAGE;
JUNCTION LEAKAGE CURRENT;
MULTILEVEL FLASH CELL DESIGN;
VOLTAGE DROP;
NONVOLATILE STORAGE;
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EID: 0029714969
PISSN: 07431562
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (12)
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References (4)
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