A double-level-Vth select gate array architecture for multilevel NAND flash memories

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 4, 1996, Pages 602-609

  Takeuchi, Ken ^a,b   Tanaka, Tomoharu ^a,c   Nakamura, Hiroshi ^a,d  

^a TOSHIBA CORPORATION   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c UNIVERSITY OF TSUKUBA   (Japan)

^d OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DISTORTION; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; NAND CIRCUITS; VOLTAGE CONTROL;

ARRAY ARCHITECTURE; ARRAY NOISE; INTERBITLINE CAPACITIVE COUPLING NOISE; MULTILEVEL FLASH MEMORIES; THRESHOLD VOLTAGE DISTRIBUTION; THRESHOLD VOLTAGE FLUCTUATION;

SEMICONDUCTOR STORAGE;

EID: 0030123707     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.499738     Document Type: Article

References (9)

1. G. J. Hemink, T. Tanaka, T. Endoh, S. Aritome, and R. Shirota, "Fast and accurate programming method for multilevel NAND flash EEPROM's," in Symp. VLSI Technology Dig. Tech. Papers, June 1995, pp. 129-130.
2. t distribution," in Symp. VLSI Circuits Dig. Tech. Papers, June 1990, pp. 105-106.
3. T. Tanaka, Y. Tanaka, H. Nakamura; H. Oodaira, S. Aritome, R. Shirota, and F. Masuoka, "A quick intelligent program architecture for 3 V-only NAND-EEPROM's," in Symp. VLSI Circuits Dig. Tech. Papers, June 1992, pp. 20-21.
4. K. D. Suh, B. H. Suh, Y. H. Lim, J. K. Kim, Y. J. Choi, Y. N. Koh, S. S. Lee, S. C. Kwon, B. S. Choi, J. S. Yum, J. H. Choi, J. R. Kim, and H. K. Lim, "A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme," in ISSCC Dig. of Tech. Papers, Feb. 1995, pp. 128-129.
5. T. Tanaka, Y. Tanaka, H. Nakamura, K. Sakui, H. Oodaira, R. Shirota K. Ohuchi F. Masuoka, and H. Hara, "A quick intelligent programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory," IEEE J. Solid-State Circuits, vol. 29, pp. 1366-1373, Nov. 1994.
6. A. Baker, R. Alexis, S. Bell, V. Dalvi, R. Durante, E. Baer, M. Fandrich, O. Jungroth, J. Kreifels, M. Landgraf, K. Lee, H. Pon, M. Rashid, R. Rozman, J. Tsang, K. Underwood, and C. Yarlagadda, "A 3.3 V 16 Mb flash memory with advanced write automation," in ISSCC Dig. of Tech. Papers, Feb. 1994, pp. 146-147.
7. th select gate array architecture for multilevel NAND flash memories," in Symp. VLSI Circuits Dig. Tech. Papers, June 1995, pp. 69-70.
8. 2 self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROM's," IEDM Tech. Dig., pp. 61-64, Dec. 1994.
9. S. Aritome, R. Shirota, G. J. Hemink, T. Endoh, and F. Masuoka, "Reliability issues of flash memory cells," Proc. IEEE, vol. 81, no. 5, pp. 776-788, May 1993.