Program word-line voltage generator for multilevel flash memories

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2000, Pages 1030-1033

  Khouri, Osama ^a,b   Micheloni, Rino ^a   Sacco, Andrea ^a   Campardo, Giovanni ^a   Torelli, Guido ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

4-LEVEL; CURRENT CONSUMPTION; DISCHARGE CIRCUITS; LINE VOLTAGE; MULTILEVEL FLASH MEMORY; RESISTIVE FEEDBACK; SETTLING TIME; SILICON AREA; WAVE FORMS;

ELECTRIC POTENTIAL; VOLTAGE REGULATORS;

FLASH MEMORY;

EID: 33646852105     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2000.913051     Document Type: Conference Paper

References (8)

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2. B. Ricco, et al., "Nonvolatile multilevel memories for digital applications" - Proceedings of the IEEE, Vol.86, No.12, Dec. 1998, pp. 2399-2421.
3. P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, eds., Flash memories. Norwell, MA: Kluwer Academic Publishers, 1999.
4. C. Calligaro, A. Manstretta, A. Modelli, and G. Torelli, "Technological and design constraints for multilevel flash memories", in Proc. Third IEEE Int. Conf. on Electronics, Circuits, and Systems, pp. 1005-1008, Oct. 1996.
5. K. Takeuchi, T. Tanaka, and T. Tanzawa, "A multiple cell architecture for high-speed programming multilevel NAND flash memories", IEEE J. Solid-State Circuits, vol.33, no.8, Aug. 1998, pp. 1228-1237.
6. O. Khouri, R. Micheloni, and G. Torelli., "Very fast recovery word-line voltage regulator for multilevel nonvolatile memories", in Proc. Third IMACS/IEEE International Multiconference on Circuits, Communications and Computers, Athens, Greece, June 1999.
7. G. Campardo, et al., "A 40mm2 3V 50MHz 64Mb 4-level cell NOR-type Flash memory", in 2000 IEEE International Solid-State Circuits Conference Dig. Tech. Papers, San Francisco, California, Feb. 2000, pp. 274-275.
8. J. Dickson, "On-chip high voltage generation in NMOS integrated circuits using an improved voltage multiplier technique ", IEEE J. Solid-State Circuits, vol.SC-11, no.3, June 1976, pp. 374-378.