A newwrite/erase method to improve the read disturb characteristics based on the decay phenomena of stress leakage current for flash memories

IEEE Transactions on Electron Devices

Volumn 45, Issue 1, 1998, Pages 98-104

  Endoh, Tetsuo ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE CURRENTS; LOGIC GATES;

FLASH MEMORIES; WRITE/READ METHOD;

DATA STORAGE EQUIPMENT;

EID: 0031699487     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.658817     Document Type: Article

References (8)

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3. T. Endoh,R. Shirota, S. Aritome, and F. Masuoka, "A study of high-performance NAND structured EEPROMS," IECE Trans. Electron., vol. E75-C, pp. 1351-1357, 1992.
4. D. A.Baglee and M. C. Smayling, "The effects of write/erase cycling on data loss in EEPROM's," in IEDM Tech. Dig., 1985, p. 624.
5. 2 films," IEEE Trans. Electron Devices, vol. 38, p. 527, 1991.
6. R. Rofanand C. Hu, "Stress-induced oxide leakage," IEEE Electron Device Lett., vol. 12, p. 632, 1991.
7. D. J.Dumin and G. A. Brown, "Stress induced changes in the I-V characteristics of 10 nm thick tunnel oxides," in NVSM Workshop Dig., 1989, p. 30.
8. T. Endoh,K. Shimizu, H. Iizuka, S. Watanabe, and F. Masuoka, "A new write/erase method for the reduction of the stress-induced leakage current based on the deactivation of step tunneling sites for Flash memories," in IEDM Tech. Dig., 1994, pp. 49-52.