An overview of Flash architectural developments

Proceedings of the IEEE

Volumn 91, Issue 4, 2003, Pages 523-535

  Campardo, Giovanni ^a,b   Scotti, Marco ^b   Scommegna, Salvatrice ^b   Pollara, Sebastiano ^b   Silvagni, Andrea ^b  

^a IEEE   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

Access time; Automatic test equipment (ATE); Boost; Charge pump; Chip scaled package (CSP); Decoders; Direct memory access (DMA); Drain stress; Dual in line (DIL); Electrical stress; Electrical wafer sort (EWS); Erasable programmable ROM (EPROM)

Indexed keywords

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; ELECTRONIC EQUIPMENT; MICROPROCESSOR CHIPS; PROM;

ACCESS TIME; AUTOMATIC TEST EQUIPMENT (ATE); BOOST; CHARGE PUMP; CHIP SCALED PACKAGE (CSP); DIRECT MEMORY ACCESS (DMA); DRAIN STRESS; DUAL IN-LINE (DIL); ELECTRICAL STRESS; ELECTRICAL WAFER SORT (EWS);

FLASH MEMORY;

EID: 20444483395     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2003.811705     Document Type: Review

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