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Volumn , Issue , 2004, Pages 111-116

Do we need anything more than single bit error correction (ECC)?

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR DETECTION; ECC TECHNOLOGY; FAULT TOLERANT METHODS; LOGICAL CORRECTION;

EID: 10044253304     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2004.1327993     Document Type: Conference Paper
Times cited : (35)

References (8)
  • 1
    • 0018021595 scopus 로고
    • Multiple word/bit line redundancy for semiconductor memories
    • October
    • S.E. Schuster, "Multiple word/bit line redundancy for semiconductor memories," IEEE Journal of Solid State Circuits, vol. Sc-13, no. 5, pp. 698-703, October 1978.
    • (1978) IEEE Journal of Solid State Circuits , vol.SC-13 , Issue.5 , pp. 698-703
    • Schuster, S.E.1
  • 2
    • 0008734381 scopus 로고
    • A 30ns 64Mb DRAM with built-in self-test and repair function
    • February
    • Koike, H., et al., "A 30ns 64Mb DRAM with Built-in Self-Test and Repair Function," Int'l Solid State Circuits Conference., pp 150-151, February 1992
    • (1992) Int'l Solid State Circuits Conference , pp. 150-151
    • Koike, H.1
  • 3
    • 0027610855 scopus 로고
    • Built-in self diagnosis for repairable embedded RAMs
    • June
    • Trueuer, R. et.al., "Built-in Self Diagnosis for Repairable Embedded RAMs," IEEE Design and Test of Computers. Pp 24-33, June 1993
    • (1993) IEEE Design and Test of Computers , pp. 24-33
    • Trueuer, R.1
  • 4
    • 0027612119 scopus 로고
    • Design of a self-testing and self-repairing structure for highly hierarchical ultra large capacity memory chips
    • June
    • Chen, T., et.al., "Design of a Self-testing and Self-repairing Structure for Highly Hierarchical Ultra large Capacity Memory Chips," IEEE Trans. On VLSI Sytesm, pp 88-97, vol 1, No. 2, June 1993
    • (1993) IEEE Trans. on VLSI Sytesm , vol.1 , Issue.2 , pp. 88-97
    • Chen, T.1
  • 5
    • 0033346869 scopus 로고    scopus 로고
    • An algorithm for row-column self-repair of RAMs and its implementation in the alpha 21264
    • Paper 123
    • Dilip K. Bhavsar "An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264", International Test Conference, Paper 123 pp.311-318, 1999
    • (1999) International Test Conference , pp. 311-318
    • Bhavsar, D.K.1
  • 6
    • 10044223348 scopus 로고    scopus 로고
    • A dynamically reconfigurable cache to improve yield in nanometer technologies
    • Amit Agarwal, Bipul, et. al., International On Line Test Symposium 2004 "A Dynamically Reconfigurable Cache to Improve Yield in Nanometer Technologies"
    • International on Line Test Symposium 2004
    • Agarwal, A.1    Bipul2
  • 7
    • 10044273061 scopus 로고    scopus 로고
    • RASUM II: Advanced availability features & capabilities of intel enterprise products
    • Feb
    • Irwinder Singh, RASUM II: Advanced Availability Features & Capabilities of Intel Enterprise Products, Intel Developer's Forum, Feb 2004
    • (2004) Intel Developer's Forum
    • Singh, I.1
  • 8
    • 84907709834 scopus 로고    scopus 로고
    • Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies
    • Hans Tuinhout, Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies, ESSDERC 2002
    • ESSDERC 2002
    • Tuinhout, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.