Do we need anything more than single bit error correction (ECC)?

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 2004, Pages 111-116

  Spica, Michael ^a   Mak, T M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR DETECTION; ECC TECHNOLOGY; FAULT TOLERANT METHODS; LOGICAL CORRECTION;

ACCELERATION; ALGORITHMS; BIT ERROR RATE; CACHE MEMORY; COSTS; DATA STORAGE EQUIPMENT; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; TRANSISTORS;

ERROR CORRECTION;

EID: 10044253304     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2004.1327993     Document Type: Conference Paper

References (8)

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3. Trueuer, R. et.al., "Built-in Self Diagnosis for Repairable Embedded RAMs," IEEE Design and Test of Computers. Pp 24-33, June 1993
4. Chen, T., et.al., "Design of a Self-testing and Self-repairing Structure for Highly Hierarchical Ultra large Capacity Memory Chips," IEEE Trans. On VLSI Sytesm, pp 88-97, vol 1, No. 2, June 1993
5. Dilip K. Bhavsar "An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264", International Test Conference, Paper 123 pp.311-318, 1999
6. Amit Agarwal, Bipul, et. al., International On Line Test Symposium 2004 "A Dynamically Reconfigurable Cache to Improve Yield in Nanometer Technologies"
7. Irwinder Singh, RASUM II: Advanced Availability Features & Capabilities of Intel Enterprise Products, Intel Developer's Forum, Feb 2004
8. Hans Tuinhout, Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies, ESSDERC 2002