A novel dimensionally-decomposed router for on-chip communication in 3D architectures

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2007, Pages 138-149

  Kim, Jongman ^a   Nicopoulos, Chrysostomos ^a   Park, Dongkook ^a   Das, Reetuparna ^a   Xie, Yuan ^a   Narayanan, Vijaykrishnan ^a   Yousif, Mazin S ^b   Das, Chita R ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

3D architecture; 3D integration; Network on chip (NoC)

Indexed keywords

3D ARCHITECTURE; 3D INTEGRATION; NETWORK-ON-CHIP (NOC);

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; TRANSISTORS;

ROUTERS;

EID: 35348908288     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1250662.1250680     Document Type: Conference Paper

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